公开(公告)号：IL281734D0

公开(公告)日：2021-05-31

申请号：IL28173421

申请日：2021-03-22

Applicant: IBM ,  BRUCE CONRAD GIAMEI ,  MARTIN RECKTENWALD ,  DONALD W SCHMIDT ,  TIMOTHY SLEGEL ,  ADITYA N PURANIK ,  MARK S FARRELL ,  CHRISTIAN JACOBI ,  JONATHAN D BRADBURY ,  CHRISTIAN ZOELLIN

Inventor： BRUCE CONRAD GIAMEI ,  MARTIN RECKTENWALD ,  DONALD W SCHMIDT ,  TIMOTHY SLEGEL ,  ADITYA N PURANIK ,  MARK S FARRELL ,  CHRISTIAN JACOBI ,  JONATHAN D BRADBURY ,  CHRISTIAN ZOELLIN

IPC: G06F9/30 ,  G06F9/38

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：GB2578070B

公开(公告)日：2020-09-09

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：GB2577468B

公开(公告)日：2020-08-05

申请号：GB202000448

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  CHRISTIAN JACOBI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS

IPC: G06F12/0875 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1027

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

公开(公告)号：GB2578070A

公开(公告)日：2020-04-15

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：GB2528901B

公开(公告)日：2017-02-08

申请号：GB201413750

申请日：2014-08-04

Applicant: IBM

Inventor： UWE BRANDT ,  MARTIN RECKTENWALD ,  CHRISTIAN JACOBI ,  MICHAEL BILLECI

IPC: G06F11/07