公开(公告)号：GB2577023B

公开(公告)日：2020-08-05

申请号：GB202000046

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：GB2577468B

公开(公告)日：2020-08-05

申请号：GB202000448

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  CHRISTIAN JACOBI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS

IPC: G06F12/0875 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1027

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

公开(公告)号：GB2577468A

公开(公告)日：2020-03-25

申请号：GB202000448

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  CHRISTIAN JACOBI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS

IPC: G06F12/0875 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1027

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

公开(公告)号：GB2577023A

公开(公告)日：2020-03-11

申请号：GB202000046

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.