公开(公告)号：GB2577023B

公开(公告)日：2020-08-05

申请号：GB202000046

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：GB2461649B

公开(公告)日：2016-12-28

申请号：GB0913420

申请日：2009-08-03

Applicant: IBM

Inventor： THOMAS SCHLIPF ,  ROLF FRITZ ,  CHRISTOPHER S SMITH ,  ULRICH MAYER ,  JAN VAN LUNTEREN

IPC: G05B19/045

公开(公告)号：GB2578070B

公开(公告)日：2020-09-09

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：GB2578070A

公开(公告)日：2020-04-15

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：GB2578410B

公开(公告)日：2020-10-28

申请号：GB202002174

申请日：2018-07-23

Applicant: IBM

Inventor： ANGEL NUNEZ MENCIAS ,  JAKOB CHRISTOPHER LANG ,  MARTIN RECKTENWALD ,  ULRICH MAYER

IPC: G06F12/14 ,  G06F12/0875

Abstract: Technology for decrypting and using a security module in a processor cache in a secure mode such that dynamic address translation prevents access to portions of the volatile memory outside of a secret store in a volatile memory.

公开(公告)号：GB2578410A

公开(公告)日：2020-05-06

申请号：GB202002174

申请日：2018-07-23

Applicant: IBM

Inventor： ANGEL NUNEZ MENCIAS ,  JAKOB CHRISTOPHER LANG ,  MARTIN RECKTENWALD ,  ULRICH MAYER

IPC: G06F12/14 ,  G06F12/0875

Abstract: Technology for decrypting and using a security module in a processor cache in a secure mode such that dynamic address translation prevents access to portions of the volatile memory outside of a secret store in a volatile memory.

公开(公告)号：GB2577023A

公开(公告)日：2020-03-11

申请号：GB202000046

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.