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公开(公告)号：JP2004355081A
公开(公告)日：2004-12-16
申请号：JP2003148751
申请日：2003-05-27
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： MATSUSHIMA SHINJI , OTANI REIKO
CPC classification number: G06F1/324 , G06F1/04 , G06F1/3203 , G06F1/325 , Y02D10/126 , Y02D50/20
Abstract: PROBLEM TO BE SOLVED: To provide a memory module that reconciles high performance and low power consumption.
SOLUTION: The memory module, which generates an internal clock synchronized with an external clock and operates on the internal clock as an operating clock, comprises a first DLL circuit for generating a first internal clock from an external clock of a first frequency bandwidth, a second DLL circuit for generating a second internal clock from an external clock of a second frequency bandwidth different from the first frequency bandwidth, and a selector for selecting either the first internal clock generated by the first DLL circuit or the second internal clock generated by the second DLL circuit to output it as the operating clock of the memory module.
COPYRIGHT: (C)2005,JPO&NCIPI-
公开(公告)号：JP2004192350A
公开(公告)日：2004-07-08
申请号：JP2002359826
申请日：2002-12-11
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： YAMAZAKI MITSUHIRO , MATSUSHIMA SHINJI , TSUKAMOTO HIDESHI , KATO ATSUYUKI
CPC classification number: G06F1/26
Abstract: PROBLEM TO BE SOLVED: To reduce power consumption at shutdown time in a computer device with a battery. SOLUTION: This computer device includes an AC adapter constituted connectably to a computer system by a power supply circuit 50 of the computer system and supplying a power to the system, a main battery 57 and a second battery 58 constituted connectably to the computer system and supplying the power to the system by discharging after charging by the power from the AC adapter 51, and a gate array circuit 62 turning off the power supply to a charger 56, or a charge circuit of the main battery 57 and/or the second battery 58, and an embedded controller 63, when the main battery 57 and/or the second battery 58 is connected to the AC adapter 51. COPYRIGHT: (C)2004,JPO&NCIPI
Abstract translation: 要解决的问题：在具有电池的计算机设备中减少关机时的功耗。
解决方案：该计算机装置包括通过计算机系统的电源电路50可连接到计算机系统的AC适配器并向系统供电，主电池57和第二电池58，其可连接到计算机 系统，并且通过来自AC适配器51的电力对充电后的放电来向系统供电，以及门阵列电路62关闭到充电器56的电源或主电池57的充电电路和/或 第二电池58和嵌入式控制器63，当主电池57和/或第二电池58连接到AC适配器51.版权所有（C）2004，JPO＆NCIPI
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公开(公告)号：JPH0997128A
公开(公告)日：1997-04-08
申请号：JP24715295
申请日：1995-09-26
Applicant: IBM
Inventor： MATSUSHIMA SHINJI , KONO SEIICHI , NAKANO MASATAKE , SHIRAISHI YUICHI
Abstract: PROBLEM TO BE SOLVED: To provide a superior information processing system which can drop or stop the operation frequency of CPU at appropriate timing even while asynchronous communication is executed with a peripheral equipment. SOLUTION: This system includes a CPU 11 which can be operated at a regular mode and a power saving mode whose power consumption is lower than the regular mode, one or more peripheral equipments 17, 23, buses 12, 16 and 22 for making communication between the peripheral equipments 17, 23 and CPU 11, a bus cycle detection means for monitoring a bus cycle on the buses, a state judgment means for deciding the operation mode of the CPU 11 in a specified bus cycle detected by the bus cycle detection means and a signal generation means for transmitting a control signal for switching the operation mode based on a judgment result by the state judgment means to the CPU 11.
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公开(公告)号：JP2006133895A
公开(公告)日：2006-05-25
申请号：JP2004319639
申请日：2004-11-02
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： MATSUSHIMA SHINJI , SASAKI TAKESHI , UCHIDA HIROYUKI
Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of an information processor without making its processing performance lower than before. SOLUTION: The information processor that controls data transfer between devices is provided having an operational mode determining part for determining whether the information processor is to be operated in a normal mode or a power-saving mode according to the state of the power of the information processor, and a data transfer setting part that, when the information processor is determined to be operated in the power-saving mode, compares the state of the information processor in the mode with the state of the processor in the normal mode and sets the number of signal lines used in the data transfer at a smaller value. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：降低信息处理器的功耗，而不会使处理性能比以前低。 提供了控制设备之间的数据传输的信息处理器，其具有操作模式确定部分，用于根据电源的状态来确定信息处理器是以正常模式还是节电模式操作 信息处理器和数据传送设置部分，当确定信息处理器在省电模式下操作时，将模式中的信息处理器的状态与正常模式下的处理器的状态进行比较，并设置 在数据传输中使用的信号线的数量较小。 版权所有（C）2006，JPO＆NCIPI
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Patent Agency Ranking15.发明专利Computer system, method for controlling changeover of system operation state, and method and program for controlling power supply to peripheral device 有权计算机系统，用于控制系统操作状态变更的方法以及用于控制对外围设备供电的方法和程序
公开(公告)号：JP2005004544A
公开(公告)日：2005-01-06
申请号：JP2003168363
申请日：2003-06-12
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： INUI TAKASHI , KONO SEIICHI , NOMURA MASAHIKO , MATSUSHIMA SHINJI
CPC classification number: G06F1/3203
Abstract: PROBLEM TO BE SOLVED: To protect various devices of a computer from physical shocks by controlling the changeover of a system state in ACPI (advanced configuration and power interface) or the like on the basis of the existence of physical motion such as vibration and movement of the computer. SOLUTION: An embedded controller 41 judges whether a computer device body performs motion (vibration, movement, rotation, etc.) or not on the basis of acceleration information obtained by an acceleration sensor 60 built in the computer device body. When the computer device body performs motion, the embedded controller 41 controls the changeover of a system state by an I/O bridge so as to be temporarily extended. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：通过基于诸如振动的物理运动的存在来控制ACPI（高级配置和功率接口）等中的系统状态的切换来保护计算机的各种设备免受物理冲击 和运动的电脑。 解决方案：嵌入式控制器41基于内置在计算机设备主体中的加速度传感器60获得的加速度信息来判断计算机设备主体是否执行运动（振动，移动，旋转等）。 当计算机设备主体执行运动时，嵌入式控制器41通过I / O桥控制系统状态的切换以暂时延长。 版权所有（C）2005，JPO＆NCIPI
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16.发明专利
公开(公告)号：JP2004326236A
公开(公告)日：2004-11-18
申请号：JP2003117054
申请日：2003-04-22
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： KONO SEIICHI , MATSUSHIMA SHINJI
CPC classification number: G06F1/3243 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
Abstract: PROBLEM TO BE SOLVED: To lower power consumption of an information processing device further by effectively combining a technology for changing an operation frequency and an operation voltage of a central processing unit according to a computing operation load and a technology for lowering power consumption by stopping clock supply to the central processing unit together. SOLUTION: In this information processing device provided with the central processing unit having an instruction execution part executing an instruction, the central processing unit is provided with an ordinary mode for operating the instruction execution part and an execution stopping mode for stopping the instruction execution part. This information processing device is provided with a voltage control part, which makes the instruction execution part operate a voltage lowering instruction for a shift to a low voltage operation mode lowering an operation voltage of the central processing unit in comparison with that in the ordinary mode when the central processing unit is shifted from the ordinary mode to the execution stopping mode, and a mode control part shifting the central processing unit to a low voltage operation stopping mode stopping the instruction execution part with the operation voltage of the low voltage operation mode when the central processing unit is shifted to the low voltage operation mode by the voltage control part. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：通过根据计算操作负载和用于降低功耗的技术有效地组合用于改变中央处理单元的操作频率和操作电压的技术，进一步降低信息处理设备的功耗 通过将中央处理单元的时钟供应停止在一起。 解决方案：在具有中央处理单元的信息处理设备中，具有执行指令的指令执行部分，中央处理单元具有用于操作指令执行部分的普通模式和用于停止指令的执行停止模式 执行部分。 该信息处理装置设置有电压控制部，该指令执行部在与普通模式相比较时，使指示执行部进行与降低中央处理部的动作电压的低电压动作模式的切换的电压降低指示 中央处理单元从普通模式切换到执行停止模式，并且模式控制部分将中央处理单元移动到低电压操作停止模式，当低电压操作模式的操作电压停止时，停止指令执行部分 中央处理单元通过电压控制部分转移到低电压操作模式。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2003196083A
公开(公告)日：2003-07-11
申请号：JP2001393336
申请日：2001-12-26
Applicant: IBM
Inventor： YOSHIYAMA NORITOSHI , KONO SEIICHI , KOMIYAMA HIROHIDE , MATSUSHIMA SHINJI
Abstract: PROBLEM TO BE SOLVED: To provide a practical means for restraining electric power consumption by reducing operational performance of a CPU, and restraining the electric power consumption and generation of heat of the whole system when the CPU requires waiting time in the relationship with a device and is processing a program. SOLUTION: A command code executed by the CPU 101 and information on the operational performance when executing this command code are loaded in the CPU 101, and the operational performance of the CPU 101 is dynamically set to a value determined on the basis of the loaded information on the operational performance so that the CPU 101 executes this command code by the preset operational performance. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JPH09128107A
公开(公告)日：1997-05-16
申请号：JP27896195
申请日：1995-10-26
Applicant: IBM
Inventor： MATSUSHIMA SHINJI , KONO SEIICHI , NAKANO MASATAKE , INUI TAKASHI
Abstract: PROBLEM TO BE SOLVED: To provide a superior information processing system with a power management function which reduce the power consumption by adequately lowering or stopping the operating frequency of a CPU by providing a power-saving means which places the CPU in power-saving mode for a specific time after the end of a transaction. SOLUTION: The CPU and a peripheral equipment are driven asynchronously and while the both communicate with each other, an interruption request is generated for a handshake and the CPU should respond speedily to the interruption request. The CPU, however, is in a mere wait state for the specific period after a specific transaction ends and the timing of the generation of a next interruption request is previously known. In this wait state, the operation of the CPU is lowered to save the electric power and the CPU is put back to its normal mode before an interruption request is generated to keep the maintainability of the system.
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公开(公告)号：DE69630851D1
公开(公告)日：2004-01-08
申请号：DE69630851
申请日：1996-09-16
Applicant: IBM
Inventor： INUI TAKASHI , KAWANO SEIICHI , MATSUSHIMA SHINJI , NAKANO MASAYOSHI , SHIRAISHI YUICHI
IPC: G06F1/32
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