公开(公告)号：DE69229656D1

公开(公告)日：1999-09-02

申请号：DE69229656

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

公开(公告)号：SG46187A1

公开(公告)日：1998-02-20

申请号：SG1996000349

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.

公开(公告)号：IN179600B

公开(公告)日：1997-10-25

申请号：IN444MA1991

申请日：1991-06-10

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/28

公开(公告)号：CA2082916C

公开(公告)日：1996-04-16

申请号：CA2082916

申请日：1992-11-13

Applicant: IBM

Inventor： BLACKLEDGE JOHN WILEY JR ,  CLARKE GRANT LEACH JR ,  DAYAN RICHARD ALAN ,  LE KIMTHANH DO ,  MCCOURT PATRICK EDWARD ,  MITTELSTEDT MATTHEW TODD ,  MOELLER DENNIS LEE ,  NEWMAN PALMER EUGENE ,  RANDALL DAVE LEE ,  YODER JOANNA BERGER

IPC: G06F11/00 ,  G06F9/06 ,  G06F12/14 ,  G06F21/00 ,  G06F21/06 ,  G06F21/22 ,  G06F21/24

Abstract: This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, an erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for clearing any stored privileged access password from the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password.

公开(公告)号：AU660667B2

公开(公告)日：1995-07-06

申请号：AU1520092

申请日：1992-04-28

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/18 ,  G06F13/36 ,  G06F13/362 ,  G06F12/06 ,  G06F13/14

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

公开(公告)号：FI922348A

公开(公告)日：1992-11-29

申请号：FI922348

申请日：1992-05-22

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/38 ,  G06F1/24 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

公开(公告)号：MX9202526A

公开(公告)日：1992-11-01

申请号：MX9202526

申请日：1992-05-28

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40 ,  G06K9/26

Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.

公开(公告)号：FI922348A0

公开(公告)日：1992-05-22

申请号：FI922348

申请日：1992-05-22

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASKHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/38 ,  G06F13/40 ,  G06F

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

公开(公告)号：IT1216770B

公开(公告)日：1990-03-08

申请号：IT1955588

申请日：1988-02-26

Applicant: IBM

Inventor： LO YUAN CHANG ,  MOELLER DENNIS LEE ,  SZAREK JOHN JOSEPH

IPC: G06F12/16 ,  G06F11/22 ,  G06F12/06 ,  G11C29/00 ,  G06F

Abstract: A microcomputer system has first, low order address, memory means (17) soldered to the planar printed circuit board and can accept further memory means (18) pluggable into socket means on the board. At power on self test, the memory means are tested, and, if an error is detected in the first memory means, this memory means is disabled by directing the lowest order memory addresses to the second memory means and reducing the highest order addresses by the number of locations in the first memory means.

公开(公告)号：DE3567115D1

公开(公告)日：1989-02-02

申请号：DE3567115

申请日：1985-01-11

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F13/28

Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.