公开(公告)号：DE69620702D1

公开(公告)日：2002-05-23

申请号：DE69620702

申请日：1996-09-09

Applicant: IBM

Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

公开(公告)号：GB2324181A

公开(公告)日：1998-10-14

申请号：GB9803608

申请日：1998-02-21

Applicant: IBM

Inventor： MORENO JAIME UMBERTO ,  MOUDGILL MAYAN

IPC: G06F9/38

Abstract: A computer processing system stores sequences of instructions in memory for execution by a processor unit. An out-of-order load instruction may be created, either statically or dynamically, by moving a load instruction from its original position in a sequence of instructions to an earlier position in said sequence of instructions. The present invention maps the memory address space of the computer system into regions, and detects the incorrect execution of a load operation performed earlier than a sequentially preceding (in program order) store operation. More specifically, the apparatus detects out-of-order load operations, uses a region-based mapping table 330 to keep track of the memory regions accessed by the out-of-order load operations, detects the execution of store operations into regions accessed by out-of-order load operations, and directs the processor to execute a recovery sequence when interference among reordered operations is detected. The invention is applicable to static (Figs 1 and 2) and dynamic (Figs 3-7) reordering of memory operations.

公开(公告)号：CA2444543A1

公开(公告)日：2002-11-07

申请号：CA2444543

申请日：2002-04-26

Applicant: IBM

Inventor： GLOSSNER CLAIR JOHN III ,  ALTMAN ERIK R ,  HOKENEK ERDEM ,  MELTZER DAVID ,  MOUDGILL MAYAN

IPC: G06F9/38

Abstract: A processor for processing a first instruction form and a second instruction form of an instruction set comprises execution units (301-305) connected to an instruction fetch unit (322) for the first instruction form and a sequencer (325) for the second instruction form. The processor comprises a decode unit (323) for decoding instructions of the first instruction form into control signals for the execution units (301-305), and buffers (306-310), proximate to the execution units (301-305), for storing predecoded instructions of the second instruction form.

公开(公告)号：SG71088A1

公开(公告)日：2000-03-21

申请号：SG1998000431

申请日：1998-02-26

Applicant: IBM

Inventor： MORENO JAIME UMBERTO ,  MOUDGILL MAYAN

IPC: G06F9/38 ,  G06F9/445 ,  G06F12/02

Abstract: The present invention is an apparatus that maps the memory address space of the computer system into regions, and detects the incorrect execution of a load operation performed earlier than a sequentially preceding (in program order) store operation. The apparatus detects out-of-order load operations, uses a region-based mapping table to keep track of the memory regions accessed by the out-of-order load operations, detects the execution of store operations into regions accessed by out-of-order load operations, and generates a program exception when interference among reordered operations is detected. The invention is applicable to static and dynamic reordering of memory operations.