公开(公告)号：JP2005167251A

公开(公告)日：2005-06-23

申请号：JP2004349278

申请日：2004-12-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CYRILLE CABRAL JR ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LAVOIE CHRISTIAN ,  NARAYANAN VIJAY ,  STEEGEN AN L

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/823835

Abstract: PROBLEM TO BE SOLVED: To minimize the associated complexity and cost in fabricating a CMOS structure containing silicide contacts and metal silicide gates.
SOLUTION: The method of integrating the silicide metal of a CMOS allows incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-alignment process (salicide) and at least one lithography process. The integration method allows at least two different thicknesses of metals deposited on a semiconductor substrate such that on some of the CMOS transistors thinner silicide metals are formed and used in the formation of gate contacts, whereas on the other CMOS transistors thicker silicide metals are formed and used in the formation of metal silicide gates. The integration method of the present invention can also be used to form multiple phases of metal silicide gates by varying the metal deposition thickness thus having differing amounts of metal present during metal gate formation.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了最小化制造包含硅化物接触和金属硅化物栅极的CMOS结构的相关复杂性和成本。 解决方案：集成CMOS的硅化物金属的方法允许使用自对准工艺（自对准硅化物）和至少一个光刻工艺并入硅化物触点（S / D和栅极）和金属硅化物栅极。 积分方法允许沉积在半导体衬底上的至少两种不同厚度的金属，使得在一些CMOS晶体管上形成较薄的硅化物金属，并用于形成栅极触点，而在另一个CMOS晶体管上形成更厚的硅化物金属， 用于形成金属硅化物门。 本发明的积分方法还可用于通过改变金属沉积厚度从而在金属栅极形成期间存在不同量的金属来形成金属硅化物栅极的多相。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2008106244A3

公开(公告)日：2010-03-18

申请号：PCT/US2008051067

申请日：2008-01-15

Applicant: IBM ,  CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

Inventor： CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

IPC: H01L21/335

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

Abstract: A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

Abstract translation: 用于互补金属氧化物半导体（CMOS）器件的栅极结构（200）包括具有形成在衬底（100）上的第一栅极电介质层（102）的第一栅极堆叠（116）和形成在衬底 第一栅介质层。 第二栅极堆叠（118）包括形成在衬底上的第二栅极电介质层（102）和形成在第二栅极电介质层上的第二金属层（110）。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：JP2007165872A

公开(公告)日：2007-06-28

申请号：JP2006317816

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CALLEGARI ALESSANDRO ,  STEEN MICHELLE L ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  DORIS BRUCE B ,  CHUDZIK MICHAEL P

IPC: H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823842

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure containing a double metal gate and a method for manufacturing the same. SOLUTION: The semiconductor structure including at least one n-type field-effect transistor (nFET) and at least one p-type field-effect transistor (pFET), both transistors each including a metal gate having an nFET property and pFET property, and not including an upper portion-polysilicon gate electrode and a method for manufacturing such a semiconductor structure are provided. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供含有双金属栅极的半导体结构及其制造方法。 解决方案：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，每个都包括具有nFET特性的金属栅极和pFET 性能，并且不包括上部多晶硅栅电极和制造这种半导体结构的方法。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005328059A

公开(公告)日：2005-11-24

申请号：JP2005139334

申请日：2005-05-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOJARCZUK NESTOR A JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI ,  SUPURATEIKU GUUHA ,  NARAYANAN VIJAY

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L21/28202 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide semiconductor (CMOS) structure including an intermediate layer between a Si-containing gate electrode and a high-k gate dielectric, so that a threshold voltage and a flat-band voltage of the structure are stabilized.
SOLUTION: An insulating intermediate layer for use in the complementary metal-oxide semiconductor (CMOS) is provided in order to prevent undesirable shifts of the threshold voltage and the flat-band voltage. The insulating intermediate layer is disposed between a gate dielectric having a dielectric constant of more than 4.0 and a Si-containing gate conductor. The insulating intermediate layer comprises metal nitride capable of containing oxygen, and stabilizes the threshold voltage and the flat-band voltage. For a preferred embodiment, the insulating intermediate layer comprises aluminum nitride or aluminum oxinitride, and the gate dielectric comprises a hafnium oxide, hafnium silicate, or hafnium oxinitride. The structure is especially useful for stabilizing the threshold voltage and the flat-band voltage of a p-type field effect transistor.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供在含Si栅极电极和高k栅极电介质之间包括中间层的互补金属氧化物半导体（CMOS）结构，使得阈值电压和平带电压 的结构是稳定的。 解决方案：提供用于互补金属氧化物半导体（CMOS）的绝缘中间层，以便防止阈值电压和平带电压的不希望的偏移。 绝缘中间层设置在介电常数大于4.0的栅极电介质和含Si的栅极导体之间​​。 绝缘中间层包括能够含有氧的金属氮化物，稳定阈值电压和平带电压。 对于优选实施例，绝缘中间层包括氮化铝或氮氧化铝，栅极电介质包括氧化铪，硅酸铪或氧化铪。 该结构对于稳定p型场效应晶体管的阈值电压和平带电压特别有用。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2012099928A2

公开(公告)日：2012-07-26

申请号：PCT/US2012021664

申请日：2012-01-18

Applicant: IBM ,  AQUILINO MICHAEL V ,  BAIOCCO CHRISTOPHER V ,  CONTI RICHARD A ,  JAEGER DANIEL J ,  NARAYANAN VIJAY

Inventor： AQUILINO MICHAEL V ,  BAIOCCO CHRISTOPHER V ,  CONTI RICHARD A ,  JAEGER DANIEL J ,  NARAYANAN VIJAY

IPC: H01L21/762 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/517

Abstract: A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

Abstract translation: 提供衬底。 STI沟槽形成在衬底中。 填充材料形成在STI沟槽中，然后平坦化。 衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。 衬垫可降低高k金属栅极器件中的Vt-W效应。

公开(公告)号：WO2005024906A2

公开(公告)日：2005-03-17

申请号：PCT/US2004027327

申请日：2004-08-20

Applicant: IBM ,  WANG YUN YU ,  STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

Abstract translation: 提供了一种用于高性能器件的金属替换栅极的结构和方法。 牺牲栅极结构（260）首先形成在设置在半导体衬底（240）上的蚀刻停止层（250）上。 在牺牲栅极结构（300）的侧壁上设置一对间隔物（400）。 然后去除牺牲栅极结构（300），形成开口（600）。 接着，在开口部形成有包括诸如钨的金属的第一层（700），诸如氮化钛的扩散阻挡层（800）和诸如钨的金属的第二层（900）的金属栅极（1000） 600）之间。

公开(公告)号：DE602004022435D1

公开(公告)日：2009-09-17

申请号：DE602004022435

申请日：2004-08-20

Applicant: IBM

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL OSSINING ,  JAMISON PAUL

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

公开(公告)号：WO2009019187A3

公开(公告)日：2009-04-02

申请号：PCT/EP2008060022

申请日：2008-07-30

Applicant: IBM ,  CARTIER EDUARD ALBERT ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI ,  LINDER BARRY PAUL ,  DORIS BRUCE

Inventor： CARTIER EDUARD ALBERT ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI ,  LINDER BARRY PAUL ,  DORIS BRUCE

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators (10, 11) and metal containing gates. The metal layers (70, 71) of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication is simplified, requiring a reduced number of masks. Also, as a further consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. Device thresholds are adjusted by the choice of the common metal material and oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

Abstract translation: 公开了具有高k介质栅绝缘体（10,11）和含金属栅极的PFET和NFET器件的FET器件结构。 NFET和PFET器件中的栅极的金属层（70,71）已经由单个公共金属层制造。 由于单个普通金属，器件制造简化，需要减少数量的掩模。 此外，作为使用单层金属作为两种类型的器件的栅极的进一步的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 通过选择普通金属材料和高k电介质的氧气曝光来调节器件阈值。 阈值是针对低功耗设备操作的。

公开(公告)号：WO2005083780A2

公开(公告)日：2005-09-09

申请号：PCT/US2005005565

申请日：2005-02-22

Applicant: IBM ,  AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

Inventor： AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

Abstract translation: 本发明提供了互补金属氧化物半导体集成工艺，由此在栅极电介质顶上制造多个硅化金属栅极。 不管硅化物金属栅极的尺寸如何，使用本发明的集成方案形成的每个硅化金属栅极具有相同的硅化物金属相和基本相同的高度。 本发明还提供了形成具有硅化触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：WO2011090907A3

公开(公告)日：2012-03-08

申请号：PCT/US2011021326

申请日：2011-01-14

Applicant: IBM

Inventor： ADUSUMILLI PRANEET ,  CALLEGARI ALESSANDRO ,  CHANG JOSEPHINE B ,  CHOI CHANGHWAN ,  FRANK MARTIN MICHAEL ,  GUILLOM MICHAEL ,  NARAYANAN VIJAY

IPC: H01L21/8232 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/772

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513

Abstract: A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. Sn one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer, In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

Abstract translation: 一种场效应晶体管器件和方法，其包括覆盖半导体衬底的半导体衬底，介电栅极层，优选高介电常数栅极层和覆盖栅极电介质层的导电氧阻挡层。 在一个实施例中，在栅介质层和氧阻挡层之间存在导电层。在另一个实施例中，在氧阻隔层上存在低电阻率金属层。