公开(公告)号：JP2012054555A

公开(公告)日：2012-03-15

申请号：JP2011187435

申请日：2011-08-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICKY S AMOS ,  BOYD DIANE C ,  CYRIL CABRAL JR ,  RICHARD D KAPLAN ,  JAKUB T KEDZIERSKI ,  VICTOR KU ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  ANNE L ZEUGEN ,  SERENDRA MAHESWARAN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal oxide semiconductor integration process that allows a plurality of silicide metal gates to be prepared on a gate dielectric.SOLUTION: There is provided a CMOS silicide metal gate integration method capable of eliminating a demerit of generation of variations in the height of poly Si gate stock which varies a silicide metal gate phase. The integration method minimizes the complexity of the process, thereby restraining the manufacturing cost of a CMOS transistor from increasing.

Abstract translation: 要解决的问题：提供允许在栅极电介质上制备多个硅化物金属栅极的互补金属氧化物半导体集成工艺。 解决方案：提供了一种CMOS硅化物金属栅极集成方法，其能够消除改变硅化物金属栅极相的多晶硅栅极原料的高度变化的缺点。 该集成方法最小化了工艺的复杂性，从而抑制了CMOS晶体管的制造成本增加。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：WO2005091186A8

公开(公告)日：2006-10-26

申请号：PCT/EP2005051089

申请日：2005-03-10

Applicant: IBM ,  IBM UK ,  LI YING ,  YU XIU LAN ,  CHEN YING

Inventor： LI YING ,  YU XIU LAN ,  CHEN YING

IPC: G06F9/42 ,  G06F11/20

CPC classification number: G06F11/1482

公开(公告)号：WO2007033922B1

公开(公告)日：2007-06-21

申请号：PCT/EP2006066298

申请日：2006-09-12

Applicant: IBM ,  IBM UK ,  CHEN YING ,  LI YING ,  QIU JIE

Inventor： CHEN YING ,  LI YING ,  QIU JIE

IPC: G06F11/34 ,  G06F9/50

CPC classification number: G06F9/5061 ,  G06F9/5083 ,  G06F11/3433 ,  G06F11/3447 ,  G06F2201/88 ,  G06F2209/508

Abstract: A method for dynamically adjusting resources among a plurality of co-existing applications comprises the steps of : building a relation model (S101) between a request number and resource consumption of said plurality of applications; obtaining at multiple sampling moments a request number (S102) and resource consumption (S103) of each of said plurality of applications; calculating resource consumption ratio (S104) of each of said plurality of applications; and analyzing resource consumption of a plurality of currently co-existing applications (S106).

Abstract translation: 一种用于在多个共存应用程序之间动态调整资源的方法，包括以下步骤：在所述多个应用程序的请求号和资源消耗之间建立关系模型（S101） 在多个采样时刻获得所述多个应用中的每一个的请求号码（S102）和资源消耗（S103） 计算所述多个应用中的每一个的资源消耗比率（S104） 并分析多个当前共存的应用程序的资源消耗（S106）。

公开(公告)号：WO2007033922A3

公开(公告)日：2007-05-10

申请号：PCT/EP2006066298

申请日：2006-09-12

Applicant: IBM ,  IBM UK ,  CHEN YING ,  LI YING ,  QIU JIE

Inventor： CHEN YING ,  LI YING ,  QIU JIE

IPC: G06F11/34 ,  G06F9/50

CPC classification number: G06F9/5061 ,  G06F9/5083 ,  G06F11/3433 ,  G06F11/3447 ,  G06F2201/88 ,  G06F2209/508

Abstract: A method for dynamically adjusting resources among a plurality of co-existing applications comprises the steps of : building a relation model (S101) between a request number and resource consumption of said plurality of applications; obtaining at multiple sampling moments a request number (S102) and resource consumption (S103) of each of said plurality of applications; calculating resource consumption ratio (S104) of each of said plurality of applications; and analyzing resource consumption of a plurality of currently co-existing applications (S106).

Abstract translation: 一种用于在多个共存应用程序之间动态调整资源的方法包括以下步骤：构建所述多个应用的​​请求号码与资源消耗之间的关系模型（S101）; 在多个采样时刻获得所述多个应用中的每一个的请求号码（S102）和资源消耗（S103）; 计算所述多个应用中的每一个的资源消耗比（S104）; 并分析多个当前共存的应用的资源消耗（S106）。

公开(公告)号：EP1864319A4

公开(公告)日：2009-11-18

申请号：EP06748845

申请日：2006-03-29

Applicant: IBM

Inventor： BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

IPC: H01L21/26

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.

公开(公告)号：EP2697738A4

公开(公告)日：2015-06-24

申请号：EP12770637

申请日：2012-04-15

Applicant: IBM

Inventor： HAAS NORMAN ,  LI YING ,  OTTO CHARLES A ,  PANKANTI SHARATHCHANDRA

IPC: G06K9/00 ,  B61K9/08 ,  B61L23/04

CPC classification number: G06K9/00 ,  B61L23/047 ,  B61L23/048

公开(公告)号：EP1834350A4

公开(公告)日：2009-06-17

申请号：EP05853245

申请日：2005-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

公开(公告)号：WO2005024906A2

公开(公告)日：2005-03-17

申请号：PCT/US2004027327

申请日：2004-08-20

Applicant: IBM ,  WANG YUN YU ,  STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

Abstract translation: 提供了一种用于高性能器件的金属替换栅极的结构和方法。 牺牲栅极结构（260）首先形成在设置在半导体衬底（240）上的蚀刻停止层（250）上。 在牺牲栅极结构（300）的侧壁上设置一对间隔物（400）。 然后去除牺牲栅极结构（300），形成开口（600）。 接着，在开口部形成有包括诸如钨的金属的第一层（700），诸如氮化钛的扩散阻挡层（800）和诸如钨的金属的第二层（900）的金属栅极（1000） 600）之间。

公开(公告)号：EP1668706A4

公开(公告)日：2008-11-05

申请号：EP04786558

申请日：2004-08-20

Applicant: IBM

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

公开(公告)号：WO2011043870A3

公开(公告)日：2011-06-23

申请号：PCT/US2010046567

申请日：2010-08-25

Applicant: IBM ,  LI YING ,  NARASIMHA SHREESH ,  RAUSCH WERNER A

Inventor： LI YING ,  NARASIMHA SHREESH ,  RAUSCH WERNER A

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC classification number: H01L29/78615 ,  H01L21/74 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66772

Abstract: Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.

Abstract translation: 公开了具有FET区域，体接触区域和STI区域的体硅层上的SOI器件。 FET区域由SOI层和上覆栅极构成。 STI区域包括将SOI器件与相邻SOI器件分开的第一STI层。 身体接触区域包括SOI层的延伸部，延伸部上的第​​二STI层和与延伸部接触的身体接触部。 第一和第二STI层是连续的和不同的厚度，以便形成分级STI。