ELECTRONIC STRUCTURE HAVING IN-SITU RESISTORS
    2.
    发明申请
    ELECTRONIC STRUCTURE HAVING IN-SITU RESISTORS 审中-公开
    具有现场电阻的电子结构

    公开(公告)号:WO0231867A3

    公开(公告)日:2002-10-17

    申请号:PCT/GB0104430

    申请日:2001-10-05

    Applicant: IBM IBM UK

    CPC classification number: H01L28/20 H01L27/0688

    Abstract: Electronic structure that has in-situ formed resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The structure may be combined with a capacitor network to form RC circuits.

    Abstract translation: 具有原位形成的电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件,形成在顶部上并与第一多个导电元件中的至少一个电连通的多个电阻通孔,以及 形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 该结构还可以形成为多电平配置,使得多电平电阻器可以串联连接以提供更大的电阻值。 该结构可以与电容器网络组合以形成RC电路。

    GATE STRUCTURE OF SEMICONDUCTOR DEVICE
    5.
    发明专利

    公开(公告)号:JP2002124672A

    公开(公告)日:2002-04-26

    申请号:JP2001193470

    申请日:2001-06-26

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a gate structure for MOSFETs for application of the CMOS technology, etc., which is durable against high temperature processes such as junction activation, etc., and reduces the gate propagation delay. SOLUTION: The gate structure 10 has an insulation layer 14 on a semiconductor substrate 12, and a polysilicon gate electrode 16 on the insulation layer 14. The gate structure 10 comprises a diffused barrier layer 20 having semi- insulative characteristics on the gate electrode 16, and a gate conductor 18 on the barrier layer 20. The conductor 18 is electrically contacted to the gate electrode 16. The constitution and the thickness of the barrier layer 20 are adjusted so as to effectively block the diffusion and the mixing between the gate conductor 18 and the gate electrode 16, but realize a capacitive coupling and/or a leak current not so increasing the gate propagation delayer of the gate surface 10.

    STRUCTURE AND METHOD FOR METAL REPLACEMENT GATE OF HIGH PERFORMANCE DEVICE
    7.
    发明申请
    STRUCTURE AND METHOD FOR METAL REPLACEMENT GATE OF HIGH PERFORMANCE DEVICE 审中-公开
    高性能设备金属更换门的结构与方法

    公开(公告)号:WO2005024906A2

    公开(公告)日:2005-03-17

    申请号:PCT/US2004027327

    申请日:2004-08-20

    CPC classification number: H01L29/66545 H01L21/28079 H01L29/4958

    Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

    Abstract translation: 提供了一种用于高性能器件的金属替换栅极的结构和方法。 牺牲栅极结构(260)首先形成在设置在半导体衬底(240)上的蚀刻停止层(250)上。 在牺牲栅极结构(300)的侧壁上设置一对间隔物(400)。 然后去除牺牲栅极结构(300),形成开口(600)。 接着,在开口部形成有包括诸如钨的金属的第一层(700),诸如氮化钛的扩散阻挡层(800)和诸如钨的金属的第二层(900)的金属栅极(1000) 600)之间。

    PLATE THROUGH MASK FOR GENERATING ALIGNMENT MARKS OF MIM CAPACITORS
    8.
    发明申请
    PLATE THROUGH MASK FOR GENERATING ALIGNMENT MARKS OF MIM CAPACITORS 审中-公开
    通过面板生成MIM电容器的对准标记

    公开(公告)号:WO2004049407A3

    公开(公告)日:2004-10-14

    申请号:PCT/EP0312654

    申请日:2003-11-12

    Abstract: A method of manufacturing a semiconductor device, comprising depositing an insulating layer over a workpiece, and defining a pattern for at least one alignment marks, at least one MIM capacitor, and a plurality of conductive lines within the insulating layer. A resist is formed over the alignment marks and MIM capacitor pattern, and a conductive material is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines. The resist is removed from over the alignment mark and MIM capacitor pattern. MIM capacitor material layers are deposited over the wafer, and the wafer is chemically-mechanically polished to form a MIM capacitor, while leaving the topography of the alignment marks visible on the surface of the wafer, so that the alignment marks may be used for alignment of subsequently deposited layers of the semiconductor device.

    Abstract translation: 一种制造半导体器件的方法,包括在工件上沉积绝缘层,并且限定用于至少一个对准标记的图案,至少一个MIM电容器和绝缘层内的多条导电线。 在对准标记和MIM电容器图案上形成抗蚀剂,并且在晶片上沉积导电材料以填充导电图案。 晶片被化学机械抛光以从绝缘层上方去除多余的导电材料并形成导电线。 从对准标记和MIM电容器图案上去除抗蚀剂。 将MIM电容器材料层沉积在晶片上,并且晶片被化学机械抛光以形成MIM电容器,同时留下在晶片表面上可见的对准标记的形貌,使得对准标记可用于对准 的后续沉积的半导体器件的层。

    THIN FILM TRANSISTOR DEVICE, AND THEIR FORMING METHOD

    公开(公告)号:JP2003229435A

    公开(公告)日:2003-08-15

    申请号:JP2003003523

    申请日:2003-01-09

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a flattened polymer transistor, and a structure thereof. SOLUTION: A completely flattened polymer thin film transistor is formed by processing a first portion of a device including a gate, a source, and a body element using a first flattened carrier. The thin film transistor is preferably formed with an organic material. For a gate dielectric a high K polymer can be employed to improve device performance. Then, a partly completed device structure is upside down, and is transferred to a second flattened carrier. A layer of wax or of a photosensitive organic material is deposited and is employed as a tentative bonding agent. A device including a body region is defined with an etching process. A contact to the device is formed with deposition of a conductive material and chemical/mechanical polishing. COPYRIGHT: (C)2003,JPO

Patent Agency Ranking