公开(公告)号：EP1397830A4

公开(公告)日：2009-03-11

申请号：EP01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，发现热处理后开路的问题，并通过使用Ti的第一衬垫层（42），随后使用CVD共形衬垫层（46） TiN，然后依次是TA或TaN的最终衬垫层（48），因此改善了通孔和下面的铜层之间的粘合性，同时将由Ti和铜之间的合金化引起的电阻的增加减少到可接受的量。

公开(公告)号：WO0231867A3

公开(公告)日：2002-10-17

申请号：PCT/GB0104430

申请日：2001-10-05

Applicant: IBM ,  IBM UK

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KWONG HON

IPC: H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0688

Abstract: Electronic structure that has in-situ formed resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The structure may be combined with a capacitor network to form RC circuits.

Abstract translation: 具有原位形成的电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件，形成在顶部上并与第一多个导电元件中的至少一个电连通的多个电阻通孔，以及 形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 该结构还可以形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 该结构可以与电容器网络组合以形成RC电路。

公开(公告)号：EP1668706A4

公开(公告)日：2008-11-05

申请号：EP04786558

申请日：2004-08-20

Applicant: IBM

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

公开(公告)号：EP1356507A4

公开(公告)日：2008-05-21

申请号：EP01996224

申请日：2001-12-30

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  BRODSKY STEPHEN BRUCE ,  CABRAL CYRIL JR ,  DOMENICUCCI ANTHONY G ,  RANSOM CRAIG MITCHELL ,  WANG YUN-YU ,  WILDMAN HORATIO S ,  WONG KWONG HON

IPC: C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44

CPC classification number: C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

Abstract: A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.

公开(公告)号：JP2002124672A

公开(公告)日：2002-04-26

申请号：JP2001193470

申请日：2001-06-26

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ALFRED ,  MANDELMAN JACK A ,  JAMMY RAJARO ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE LENNOX ,  WONG KWONG HON ,  FALTERMEIER JONATHAN

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a gate structure for MOSFETs for application of the CMOS technology, etc., which is durable against high temperature processes such as junction activation, etc., and reduces the gate propagation delay. SOLUTION: The gate structure 10 has an insulation layer 14 on a semiconductor substrate 12, and a polysilicon gate electrode 16 on the insulation layer 14. The gate structure 10 comprises a diffused barrier layer 20 having semi- insulative characteristics on the gate electrode 16, and a gate conductor 18 on the barrier layer 20. The conductor 18 is electrically contacted to the gate electrode 16. The constitution and the thickness of the barrier layer 20 are adjusted so as to effectively block the diffusion and the mixing between the gate conductor 18 and the gate electrode 16, but realize a capacitive coupling and/or a leak current not so increasing the gate propagation delayer of the gate surface 10.

公开(公告)号：JP2004080031A

公开(公告)日：2004-03-11

申请号：JP2003288276

申请日：2003-08-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  WONG KWONG HON

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545

Abstract: PROBLEM TO BE SOLVED: To offer an integrated circuit structure comprising a pair of capacitors, which respectively have metal plates separated by an insulator, and a metal-gate semiconductor transistor which is electrically connected to the capacitors.
SOLUTION: Each metal gate of a transistor and one of the metal plates of each capacitor have the same metal level in an integrated circuit structure. A more detailed description is that each capacitor described above comprises a vertical capacitor which has an upper metal plate vertically above a lower metal plate, and each metal gate of the transistor and the upper metal plate of each capacitor have the same metal level in the integrated circuit structure.
COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2005024906A2

公开(公告)日：2005-03-17

申请号：PCT/US2004027327

申请日：2004-08-20

Applicant: IBM ,  WANG YUN YU ,  STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

Abstract translation: 提供了一种用于高性能器件的金属替换栅极的结构和方法。 牺牲栅极结构（260）首先形成在设置在半导体衬底（240）上的蚀刻停止层（250）上。 在牺牲栅极结构（300）的侧壁上设置一对间隔物（400）。 然后去除牺牲栅极结构（300），形成开口（600）。 接着，在开口部形成有包括诸如钨的金属的第一层（700），诸如氮化钛的扩散阻挡层（800）和诸如钨的金属的第二层（900）的金属栅极（1000） 600）之间。

公开(公告)号：WO2004049407A3

公开(公告)日：2004-10-14

申请号：PCT/EP0312654

申请日：2003-11-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NING XIAN J ,  WONG KWONG HON

IPC: H01L21/02 ,  H01L23/544 ,  H01L27/08

CPC classification number: H01L28/40 ,  H01L23/544 ,  H01L27/0805 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device, comprising depositing an insulating layer over a workpiece, and defining a pattern for at least one alignment marks, at least one MIM capacitor, and a plurality of conductive lines within the insulating layer. A resist is formed over the alignment marks and MIM capacitor pattern, and a conductive material is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines. The resist is removed from over the alignment mark and MIM capacitor pattern. MIM capacitor material layers are deposited over the wafer, and the wafer is chemically-mechanically polished to form a MIM capacitor, while leaving the topography of the alignment marks visible on the surface of the wafer, so that the alignment marks may be used for alignment of subsequently deposited layers of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法，包括在工件上沉积绝缘层，并且限定用于至少一个对准标记的图案，至少一个MIM电容器和绝缘层内的多条导电线。 在对准标记和MIM电容器图案上形成抗蚀剂，并且在晶片上沉积导电材料以填充导电图案。 晶片被化学机械抛光以从绝缘层上方去除多余的导电材料并形成导电线。 从对准标记和MIM电容器图案上去除抗蚀剂。 将MIM电容器材料层沉积在晶片上，并且晶片被化学机械抛光以形成MIM电容器，同时留下在晶片表面上可见的对准标记的形貌，使得对准标记可用于对准 的后续沉积的半导体器件的层。

公开(公告)号：JP2004158851A

公开(公告)日：2004-06-03

申请号：JP2003359944

申请日：2003-10-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LARRY ,  KLEPEIS STANLEY ,  LU HSIAO-LING ,  MARINO JEFFREY ,  SIMON ANDREW HERBERT ,  WANG YUN-YU ,  WONG KWONG HON ,  YANG CHIH-CHAO

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To solve the problem of carbon contamination that dos not occur in circuits using oxide as dielectric, which exists in advanced technology using low-k organic-based interlayer dielectrics in copper backend integrated circuit technology. SOLUTION: A composite liner layer for the copper lines uses Ti as a bottom layer, which has property of gettering carbon and other contaminants. The known problem of Ti as reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003229435A

公开(公告)日：2003-08-15

申请号：JP2003003523

申请日：2003-01-09

Applicant: IBM

Inventor： TORISHIA L BREEN ,  CLEVENGER LAWRENCE A ,  LEWIS L SUU ,  WANG LI-KONG ,  WONG KWONG HON

IPC: H01L51/05 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786 ,  H01L35/24 ,  H01L51/00 ,  H01L51/40

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a flattened polymer transistor, and a structure thereof. SOLUTION: A completely flattened polymer thin film transistor is formed by processing a first portion of a device including a gate, a source, and a body element using a first flattened carrier. The thin film transistor is preferably formed with an organic material. For a gate dielectric a high K polymer can be employed to improve device performance. Then, a partly completed device structure is upside down, and is transferred to a second flattened carrier. A layer of wax or of a photosensitive organic material is deposited and is employed as a tentative bonding agent. A device including a body region is defined with an etching process. A contact to the device is formed with deposition of a conductive material and chemical/mechanical polishing. COPYRIGHT: (C)2003,JPO