Abstract:
In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.
Abstract:
Electronic structure that has in-situ formed resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The structure may be combined with a capacitor network to form RC circuits.
Abstract:
A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).
Abstract:
A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.
Abstract:
PROBLEM TO BE SOLVED: To provide a gate structure for MOSFETs for application of the CMOS technology, etc., which is durable against high temperature processes such as junction activation, etc., and reduces the gate propagation delay. SOLUTION: The gate structure 10 has an insulation layer 14 on a semiconductor substrate 12, and a polysilicon gate electrode 16 on the insulation layer 14. The gate structure 10 comprises a diffused barrier layer 20 having semi- insulative characteristics on the gate electrode 16, and a gate conductor 18 on the barrier layer 20. The conductor 18 is electrically contacted to the gate electrode 16. The constitution and the thickness of the barrier layer 20 are adjusted so as to effectively block the diffusion and the mixing between the gate conductor 18 and the gate electrode 16, but realize a capacitive coupling and/or a leak current not so increasing the gate propagation delayer of the gate surface 10.
Abstract:
PROBLEM TO BE SOLVED: To offer an integrated circuit structure comprising a pair of capacitors, which respectively have metal plates separated by an insulator, and a metal-gate semiconductor transistor which is electrically connected to the capacitors. SOLUTION: Each metal gate of a transistor and one of the metal plates of each capacitor have the same metal level in an integrated circuit structure. A more detailed description is that each capacitor described above comprises a vertical capacitor which has an upper metal plate vertically above a lower metal plate, and each metal gate of the transistor and the upper metal plate of each capacitor have the same metal level in the integrated circuit structure. COPYRIGHT: (C)2004,JPO
Abstract:
A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).
Abstract:
A method of manufacturing a semiconductor device, comprising depositing an insulating layer over a workpiece, and defining a pattern for at least one alignment marks, at least one MIM capacitor, and a plurality of conductive lines within the insulating layer. A resist is formed over the alignment marks and MIM capacitor pattern, and a conductive material is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines. The resist is removed from over the alignment mark and MIM capacitor pattern. MIM capacitor material layers are deposited over the wafer, and the wafer is chemically-mechanically polished to form a MIM capacitor, while leaving the topography of the alignment marks visible on the surface of the wafer, so that the alignment marks may be used for alignment of subsequently deposited layers of the semiconductor device.
Abstract:
PROBLEM TO BE SOLVED: To solve the problem of carbon contamination that dos not occur in circuits using oxide as dielectric, which exists in advanced technology using low-k organic-based interlayer dielectrics in copper backend integrated circuit technology. SOLUTION: A composite liner layer for the copper lines uses Ti as a bottom layer, which has property of gettering carbon and other contaminants. The known problem of Ti as reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper. COPYRIGHT: (C)2004,JPO
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method for a flattened polymer transistor, and a structure thereof. SOLUTION: A completely flattened polymer thin film transistor is formed by processing a first portion of a device including a gate, a source, and a body element using a first flattened carrier. The thin film transistor is preferably formed with an organic material. For a gate dielectric a high K polymer can be employed to improve device performance. Then, a partly completed device structure is upside down, and is transferred to a second flattened carrier. A layer of wax or of a photosensitive organic material is deposited and is employed as a tentative bonding agent. A device including a body region is defined with an etching process. A contact to the device is formed with deposition of a conductive material and chemical/mechanical polishing. COPYRIGHT: (C)2003,JPO