公开(公告)号：EP2519976A4

公开(公告)日：2014-02-19

申请号：EP11735025

申请日：2011-01-14

Applicant: IBM

Inventor： ADUSUMILLI PRANEET ,  CALLEGARI ALESSANDRO ,  CHANG JOSEPHINE B ,  CHOI CHANGHWAN ,  FRANK MARTIN MICHAEL ,  GUILLOM MICHAEL ,  NARAYANAN VIJAY

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513

公开(公告)号：JP2007173796A

公开(公告)日：2007-07-05

申请号：JP2006322537

申请日：2006-11-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CALLEGARI ALESSANDRO ,  VIJAY NARAYANAN ,  MICHAEL A GRIBELYUK ,  PARUCHURI VAMSI K ,  ZAFAR SUFI

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: PROBLEM TO BE SOLVED: To provide a new metal compound which is stable to heat on a gate stack containing a high-k dielectric and does not cause carbon diffusion caused in the case of a metal carbide. SOLUTION: This invention provides the metal compound which is a p-type metal having a work function of about 4.75-5.3 eV, preferably about 5 eV and comprises MO x N y stable to heat on the gate stack comprising the high-k dielectric and an interface layer, and a method for manufacturing the MO x N y metal compound. Further, the MO x N y metal compound is an extremely efficient oxygen diffusion barrier at 1,000°C, and achieves, in a p-type metal oxide semiconductor (pMOS) device, an extremely aggressive equivalent oxide film thickness (EOT) and an inversion layer thickness of 14 Å or less. In this formula, M is metal selected from Group IVB, VB, VIB and VIIB of the periodic table of the elements, x is about 5-40 atomic%, and y is about 5-40 atomic%. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供在含有高k电介质的栅极堆叠上对热稳定的新的金属化合物，并且在金属碳化物的情况下不引起碳扩散。 解决方案：本发明提供金属化合物，其为具有约4.75-5.3eV，优选约5eV的功函数的p型金属，并且包括MO x N < / SB>在包含高k电介质和界面层的栅极堆叠上的热稳定，以及用于制造金属化合物的方法。 此外，金属化合物在1000℃下是非常有效的氧扩散阻挡层，并且在p型金属氧化物半导体（pMOS）器件中实现 ，极高的等效氧化膜厚度（EOT）和反射层厚度为14或更小。 在该式中，M是选自元素周期表的IVB，VB，VIB和VIIB族的金属，x为约5-40原子％，y为约5-40原子％。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002062532A

公开(公告)日：2002-02-28

申请号：JP2001192436

申请日：2001-06-26

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO ,  PURAVIIN CHOODARI ,  JAMES PATRICK DOYLE ,  GALLIGAN EILEEN ANN ,  KATO YOSHIMINE ,  JAMES ANDREW LACEY ,  SHUI CHIN ALAN RYAN ,  MINHA RUU ,  NAKANO HIROTAKE

IPC: G02F1/1333 ,  C23C14/06 ,  C23C14/22 ,  C23C14/34 ,  G02F1/1337

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an alignment layer on a substrate. SOLUTION: The film is adhered and aligned in a single step with a method containing a step to shoot an ion-beam at the substrate with a specified incident angle and simultaneously to adhere the film to the substrate (a) and to align an atomic structure of the film in at least a specified aligning direction (b).

公开(公告)号：JP2007165872A

公开(公告)日：2007-06-28

申请号：JP2006317816

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CALLEGARI ALESSANDRO ,  STEEN MICHELLE L ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  DORIS BRUCE B ,  CHUDZIK MICHAEL P

IPC: H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823842

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure containing a double metal gate and a method for manufacturing the same. SOLUTION: The semiconductor structure including at least one n-type field-effect transistor (nFET) and at least one p-type field-effect transistor (pFET), both transistors each including a metal gate having an nFET property and pFET property, and not including an upper portion-polysilicon gate electrode and a method for manufacturing such a semiconductor structure are provided. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供含有双金属栅极的半导体结构及其制造方法。 解决方案：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，每个都包括具有nFET特性的金属栅极和pFET 性能，并且不包括上部多晶硅栅电极和制造这种半导体结构的方法。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2005029568A2

公开(公告)日：2005-03-31

申请号：PCT/US2004026811

申请日：2004-08-19

Applicant: TOKYO ELECTRON LTD ,  IBM ,  O'MEARA DAVID L ,  WAJDA CORY ,  TAKAHASHI TSUYOSHI ,  CALLEGARI ALESSANDRO ,  SCHEER KRISTEN ,  ZAFAR SUFI ,  JAMISON PAUL

Inventor： O'MEARA DAVID L ,  WAJDA CORY ,  TAKAHASHI TSUYOSHI ,  CALLEGARI ALESSANDRO ,  SCHEER KRISTEN ,  ZAFAR SUFI ,  JAMISON PAUL

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  C23C16/34 ,  H01L21/00 ,  H01L21/66

CPC classification number: H01L21/28185 ,  H01L21/02181 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31658 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method is provided for forming a microstructure with an interfacial oxide layer by using a diffusion filter layer to control the oxidation properties of a substrate associated with formation of a high-k layer into the microstructure. The diffusion filter layer controls the oxidation of the surface. The interfacial oxide layer can be formed during an oxidation process that is carried out following deposition of a high­k layer onto the diffusion filter layer, or during deposition of a high-k layer onto the diffusion filter layer.

Abstract translation: 提供了一种用于通过使用扩散过滤层来形成具有界面氧化物层的微观结构以控制与形成高k层的微结构相关联的衬底的氧化性能的方法。 扩散过滤层控制表面的氧化。 可以在氧化过程中形成界面氧化物层，该氧化工艺是在将highk层沉积到扩散过滤层上之后，或者在将高k层沉积到扩散过滤层上时进行的。

公开(公告)号：WO2011090907A3

公开(公告)日：2012-03-08

申请号：PCT/US2011021326

申请日：2011-01-14

Applicant: IBM

Inventor： ADUSUMILLI PRANEET ,  CALLEGARI ALESSANDRO ,  CHANG JOSEPHINE B ,  CHOI CHANGHWAN ,  FRANK MARTIN MICHAEL ,  GUILLOM MICHAEL ,  NARAYANAN VIJAY

IPC: H01L21/8232 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/772

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513

Abstract: A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. Sn one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer, In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

Abstract translation: 一种场效应晶体管器件和方法，其包括覆盖半导体衬底的半导体衬底，介电栅极层，优选高介电常数栅极层和覆盖栅极电介质层的导电氧阻挡层。 在一个实施例中，在栅介质层和氧阻挡层之间存在导电层。在另一个实施例中，在氧阻隔层上存在低电阻率金属层。

公开(公告)号：WO2005013348A3

公开(公告)日：2005-09-22

申请号：PCT/US2004024595

申请日：2004-07-30

Applicant: TOKYO ELECTRON LTD ,  IBM ,  O'MEARA DAVID L ,  WAJDA CORY ,  DIP ANTHONY ,  TOELLER MICHAEL ,  FURUKAWA TOSHIHARA ,  SCHEER KRISTEN ,  CALLEGARI ALESSANDRO ,  BUEHRER FRED ,  ZAFAR SUFI ,  GOUSEV EVGENI ,  CHOU ANTHONY ,  HIGGINS PAUL

Inventor： O'MEARA DAVID L ,  WAJDA CORY ,  DIP ANTHONY ,  TOELLER MICHAEL ,  FURUKAWA TOSHIHARA ,  SCHEER KRISTEN ,  CALLEGARI ALESSANDRO ,  BUEHRER FRED ,  ZAFAR SUFI ,  GOUSEV EVGENI ,  CHOU ANTHONY ,  HIGGINS PAUL

IPC: H01L21/00 ,  H01L21/314 ,  H01L21/316 ,  C23C16/30 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/318

CPC classification number: H01L21/67098 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662

Abstract: Ultra-thin oxide and oxynitride layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide and oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in Si02 layers with a thickness of about 15Å, where the thickness of the Si02 layers varies less than about 1 Åover the substrates.

Abstract translation: 使用低压处理形成超薄氧化物和氮氧化物层以实现衬底的自限氧化并提供超薄氧化物和氮氧化物。 待处理的衬底可以包含诸如氧化物层，氮氧化物层，氮化物层，高k层的初始电介质层，或者可替代地可以缺少初始电介质层。 该处理可以使用批量式处理室或者使用单晶片处理室来进行。 本发明的一个实施方案提供了Si-衬底的自限氧化，其导致厚度为约的SiO 2层，其中SiO 2层的厚度在衬底上的变化小于约1。

公开(公告)号：AU2002357054A1

公开(公告)日：2003-06-10

申请号：AU2002357054

申请日：2002-11-27

Applicant: IBM

Inventor： KIM HYUNGJUN ,  MCFEELY FENTON ,  NARAYANAN VIJAY ,  RODBELL KENNETH ,  YURKAS JOHN ,  AMOS RICKY ,  BUCHANAN DOUGLAS ,  CABRAL CYRIL JR ,  CALLEGARI ALESSANDRO ,  GUHA SUPRATIK

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/30 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

公开(公告)号：DE112010003451T8

公开(公告)日：2013-01-10

申请号：DE112010003451

申请日：2010-08-05

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO ,  BABICH KATHERINA ,  O'SULLIVAN EUGENE ,  CONNOLLY JOHN

IPC: H01L21/768 ,  H01L23/532

公开(公告)号：DE112010003451B4

公开(公告)日：2015-01-22

申请号：DE112010003451

申请日：2010-08-05

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO ,  BABICH KATHERINA ,  O'SULLIVAN EUGENE ,  CONNOLLY JOHN

IPC: H01L21/768 ,  H01L23/532

Abstract: Verfahren zum selektiven Züchten von Kohlenstoffnanoröhren (44), das folgende Schritte umfasst: Bilden (100) einer Isolierschicht (10) auf einem Substrat (12), wobei die Isolierschicht (10) eine obere Fläche (14) aufweist; Bilden (102) eines Durchgangskontaktes (18) in der Isolierschicht (10); Bilden (104) einer aktiven Metallschicht (30) auf der Isolierschicht (10); Abtragen der aktiven Metallschicht (30) von Teilen der oberen Fläche (14) mittels eines Ionenstrahls (40), der unter einem flachen Winkel auftrifft, wobei der flache Winkel in einem Bereich von –1 Grad bis –45 Grad liegt, um das Abtragen der aktiven Schicht von einem Bodenteil des Durchgangskontaktes (18) zu verhindern; Zuführen eines kohlenstoffhaltigen Gases zum Durchgangskontakt (18), um eine einzelne Kohlenstoffnanoröhre zu bilden; und Anwenden eines zweiten Ionenstrahls (42) unter einem steilen Winkel zur aktiven Metallschicht (30) innerhalb des Durchgangskontaktes (18), wobei der steile Winkel in einem Bereich von ungefähr –46 Grad bis ungefähr –90 Grad liegt, um das selektive Wachstum einer einzelnen Kohlenstoffnanoröhre (44) innerhalb des Durchgangskontaktes (18) zu ermöglichen.