公开(公告)号：GB2503438A

公开(公告)日：2014-01-01

申请号：GB201211274

申请日：2012-06-26

Applicant: IBM

Inventor： BAROWSKI HARRY ,  NIGGEMEIER TIM

IPC: G06F9/38

Abstract: An improved system (1) for pipelining out-of-order instructions combines short latency instructions into an instruction chain to match the latency of an instruction having a second latency type. The instructions care then issued together to the short instruction pipelines (30 & 40) whilst long instructions are issued to a long pipeline (50). Timing of the write back (WB) slot of the longer instruction issued to the long pipeline (50) is used to write a value to the register (10). Dependencies between short instructions are solved by forwarding data from the first instruction to the second instruction. Output from the second instruction can be written back to the register (10) or held in an auxiliary buffer before writing to the register when the register becomes available.

公开(公告)号：CA2816184A1

公开(公告)日：2012-05-03

申请号：CA2816184

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/11

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.