公开(公告)号：GB2498892A

公开(公告)日：2013-07-31

申请号：GB201308320

申请日：2011-10-21

Applicant: IBM

Inventor： HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS J ,  PAREDES STEPHAN ,  BAROWSKI HARRY

IPC: H01L25/065 ,  H01L25/10

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

公开(公告)号：GB2498310A

公开(公告)日：2013-07-10

申请号：GB201307552

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L23/50 ,  H01L23/36

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the process layer.

公开(公告)号：DE112011102966T5

公开(公告)日：2013-06-27

申请号：DE112011102966

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HARRER HUBERT ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  HUBER ANDREAS ,  NIGGEMEIER TIM ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L25/18

Abstract: Es wird ein Mechanismus zur integrierten Stromversorgung und Stromverteilung über einen Kühlkörper bereitgestellt. Der Mechanismus weist eine Prozessorschicht auf, die über eine erste Menge von Verbindungseinheiten mit einer Signalisierungs- und Eingabe/Ausgabe-Schicht (E/A-Schicht) verbunden ist, sowie einen Kühlkörper, der über eine zweite Menge von Verbindungseinheiten mit der Prozessorschicht verbunden ist. Bei dem Mechanismus weist der Kühlkörper eine Vielzahl von Nuten auf, wobei jede Nut entweder einen Pfad für Strom oder einen Pfad für Masse bereitstellt, die der Prozessorschicht zugeführt werden sollen. Bei dem Mechanismus ist der Kühlkörper nur zur Zufuhr von Strom vorgesehen und stellt den Elementen des Mechanismus keine Datenaustauschsignale bereit, und die Signalisierungs- und E/A-Schicht ist nur zum Übertragen der Datenaustauschsignale an die Prozessorschicht und zum Empfangen der Datenaustauschsignale von der Prozessorschicht vorgesehen und stellt den Elementen der Prozessorschicht keinen Strom bereit.

公开(公告)号：DE102014101114A1

公开(公告)日：2014-10-23

申请号：DE102014101114

申请日：2014-01-30

Applicant: IBM

Inventor： ECKERT MARTIN ,  HARRER HUBERT ,  STRACH THOMAS

IPC: G06F11/22

Abstract: Die Erfindung bezieht sich auf ein Verfahren zum Festlegen eines Histogramms des Leistungsrauschens eines Computersystems, wobei das Computersystem eine Skitter-Schaltung (40) mit mehreren Skitter-Bins (48) aufweist, wobei der Skitter-Bin (48) jeweils mit einer Signalleitung (49) bei einem oder mehreren Taktzyklen verbunden ist, wobei das Verfahren aufweist: (i) Verbinden jedes Skitter-Bin (48) mit einer einzelnen Skitter-Schaltung (64); (ii) Erhöhen eines Zählers (64), wenn der entsprechende Skitter-Bin (48) freigegeben ist.

公开(公告)号：CA2816184A1

公开(公告)日：2012-05-03

申请号：CA2816184

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/11

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

公开(公告)号：GB2513330A

公开(公告)日：2014-10-29

申请号：GB201307294

申请日：2013-04-23

Applicant: IBM

Inventor： STRACH THOMAS ,  ECKERT MARTIN ,  HARRER HUBERT

IPC: G01R31/317 ,  G01R29/26 ,  G01R31/30

Abstract: A power noise histogram of a computer system is determined using a skitter circuit (40) with multiple skitter bins (48), each skitter bin (48) being connected to a signal line (49) and a counter circuit (64) at one or more clock cycles. The counter is incremented when the respective skitter bin (48) is enabled. The skitter bins are calibrated to supply voltage and are used to measure a voltage distribution during computer operation. The supply voltage to the circuit may be varied and the skitter bin that fails or the lowest successful skitter bin may be determined. This may be used to set the operating voltage or a guard band voltage. The voltage distribution may be extrapolated beyond the boundaries of the range of skitter bins. The probability of failure of the computer system for a given voltage may be calculated.

公开(公告)号：GB2498892B

公开(公告)日：2014-08-20

申请号：GB201308320

申请日：2011-10-21

Applicant: IBM

Inventor： HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS J ,  PAREDES STEPHAN ,  BAROWSKI HARRY

IPC: H01L25/065 ,  H01L25/10

公开(公告)号：GB2513529A

公开(公告)日：2014-11-05

申请号：GB201220534

申请日：2012-11-15

Applicant: IBM

Inventor： HARRER HUBERT ,  DREPS DANIEL M ,  FERRAIOLO FRANK D ,  WEBEL TOBIAS ,  WEISS ULRICH ,  TONG CHING-LUNG L ,  MAK PAK-KIN

IPC: G06F1/12 ,  G06F1/08 ,  G06F13/40

Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency, the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.

公开(公告)号：GB2498310B

公开(公告)日：2014-03-12

申请号：GB201307552

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L23/50 ,  H01L23/36

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.