公开(公告)号：GB2498892A

公开(公告)日：2013-07-31

申请号：GB201308320

申请日：2011-10-21

Applicant: IBM

Inventor： HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS J ,  PAREDES STEPHAN ,  BAROWSKI HARRY

IPC: H01L25/065 ,  H01L25/10

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

公开(公告)号：GB2498310A

公开(公告)日：2013-07-10

申请号：GB201307552

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L23/50 ,  H01L23/36

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the process layer.

公开(公告)号：CA2816184A1

公开(公告)日：2012-05-03

申请号：CA2816184

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/11

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

公开(公告)号：GB2498310B

公开(公告)日：2014-03-12

申请号：GB201307552

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L23/50 ,  H01L23/36

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

公开(公告)号：GB2498892B

公开(公告)日：2014-08-20

申请号：GB201308320

申请日：2011-10-21

Applicant: IBM

Inventor： HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS J ,  PAREDES STEPHAN ,  BAROWSKI HARRY

IPC: H01L25/065 ,  H01L25/10

公开(公告)号：DE112011102966T5

公开(公告)日：2013-06-27

申请号：DE112011102966

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HARRER HUBERT ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  HUBER ANDREAS ,  NIGGEMEIER TIM ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L25/18

Abstract: Es wird ein Mechanismus zur integrierten Stromversorgung und Stromverteilung über einen Kühlkörper bereitgestellt. Der Mechanismus weist eine Prozessorschicht auf, die über eine erste Menge von Verbindungseinheiten mit einer Signalisierungs- und Eingabe/Ausgabe-Schicht (E/A-Schicht) verbunden ist, sowie einen Kühlkörper, der über eine zweite Menge von Verbindungseinheiten mit der Prozessorschicht verbunden ist. Bei dem Mechanismus weist der Kühlkörper eine Vielzahl von Nuten auf, wobei jede Nut entweder einen Pfad für Strom oder einen Pfad für Masse bereitstellt, die der Prozessorschicht zugeführt werden sollen. Bei dem Mechanismus ist der Kühlkörper nur zur Zufuhr von Strom vorgesehen und stellt den Elementen des Mechanismus keine Datenaustauschsignale bereit, und die Signalisierungs- und E/A-Schicht ist nur zum Übertragen der Datenaustauschsignale an die Prozessorschicht und zum Empfangen der Datenaustauschsignale von der Prozessorschicht vorgesehen und stellt den Elementen der Prozessorschicht keinen Strom bereit.