公开(公告)号：DE69809224D1

公开(公告)日：2002-12-12

申请号：DE69809224

申请日：1998-08-28

Applicant: IBM

Inventor： BLANC ALAIN ,  ORENGO GERARD ,  PORET MICHEL

IPC: H03M9/00 ,  H04L49/111 ,  H04Q11/04 ,  H04L12/56

Abstract: A switching apparatus comprising a centralized Switch Core (10) and at least one SCAL element for the attachment of Protocol Adapters. The Switch Core and the SCAL communicate to each other via n parallel serial links with each one transmitting a Logical Unit. Each SCAL comprises both the receive and the transmit part at least one input for receiving cells from said Protocol Adapter; a set of n FIFO queues (21-25) for storing the cells into n parallel busses; and a set of n RAM storages, with each RAM being associated with one Logical Unit. First multiplexing means (31) receive the contents of the parallel busses for performing simultaneously n WRITE operations into the n RAM storages under control of a first set of n tables ( 36-39). Second multiplexing (41) means are provided for making READ operations from said n RAM storages under control of a second set of n tables ( 46-49). By appropriate arrangement of the two sets of tables, which are chosen complementary, the cells which are conveyed through the first multiplexing means, the RAMs and the second multiplexing means are subject to a cell rearrangement enabling to introduce at least one bitmap field, thereby producing said four Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage (50-80), one particular byte is accidentally stored into one RAM available for a Write operation by means of said first set of tables, thereby causing an alteration to the normal association between said n RAMs and said n Logical Units which is then restablished by said second set of tables.

公开(公告)号：DE69114129T2

公开(公告)日：1996-06-13

申请号：DE69114129

申请日：1991-07-17

Applicant: IBM

Inventor： ABBIATE JEAN-CLAUDE ,  BLANC ALAIN ,  JEANNIOT PATRICK ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H04B14/06 ,  H03H17/06

Abstract: A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock into a train of PCM samples which includes counting means (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storing means (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and means (327, 337, 347) driven by the sigma-delta clock for incrementing the storing means with the incrementation parameter DELTA(n). At last, the decimation filter includes computing means (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storing means and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3xN input sigma-delta samples according to the formula: Since the coefficients C(n) are directly and on-line computed with the reception of the sigma-delta pulses, the decimation filter can operate for any value of the decimation parameter without requiring the use of substantial digital processing resources. The decimation filter can be used for a wide variety of different applications requiring different decimation factors.

公开(公告)号：DE69114129D1

公开(公告)日：1995-11-30

申请号：DE69114129

申请日：1991-07-17

Applicant: IBM

Inventor： ABBIATE JEAN-CLAUDE ,  BLANC ALAIN ,  JEANNIOT PATRICK ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H04B14/06 ,  H03H17/06

Abstract: A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock into a train of PCM samples which includes counting means (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storing means (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and means (327, 337, 347) driven by the sigma-delta clock for incrementing the storing means with the incrementation parameter DELTA(n). At last, the decimation filter includes computing means (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storing means and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3xN input sigma-delta samples according to the formula: Since the coefficients C(n) are directly and on-line computed with the reception of the sigma-delta pulses, the decimation filter can operate for any value of the decimation parameter without requiring the use of substantial digital processing resources. The decimation filter can be used for a wide variety of different applications requiring different decimation factors.

公开(公告)号：DE68913967T2

公开(公告)日：1994-09-22

申请号：DE68913967

申请日：1989-07-12

Applicant: IBM

Inventor： FERRY MICHEL ,  PANTANI JEAN-PIERRE ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H03M3/02

Abstract: A sigma-delta converter including a switching component (313) controlled by a first clock (308) having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes means (306, 310, 311) for generating a second clock (350) of a same frequency than the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the swithing element occur during said defined period of time. There is also included means (305) controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving the linearity and the signal-to-noise ration of the converter. The control of the said period of time allows the varying of the energy of the pulses in order to provide pulses train which, when applied to a sigma-delta decoder, provides an analog output value representative but attenuated with respect to the analog input value.