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    13.
    发明专利
    未知

    公开(公告)号：DE69305734T2

    公开(公告)日：1997-05-15

    申请号：DE69305734

    申请日：1993-06-30

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

    IPC: H04L29/06

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    14.
    发明专利
    未知

    公开(公告)号：DE69305734D1

    公开(公告)日：1996-12-05

    申请号：DE69305734

    申请日：1993-06-30

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

    IPC: H04L29/06

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    EFFICIENT POINT TO POINT AND MULTI POINT ROUTING MECHANISM FOR PROGRAMMABLE PACKET SWITCHING NODES IN HIGH SPEED DATA TRANSMISSION NETWORKS
    15.
    发明专利
    EFFICIENT POINT TO POINT AND MULTI POINT ROUTING MECHANISM FOR PROGRAMMABLE PACKET SWITCHING NODES IN HIGH SPEED DATA TRANSMISSION NETWORKS 未知

    公开(公告)号：CA2144402A1

    公开(公告)日：1995-10-15

    申请号：CA2144402

    申请日：1995-03-10

    Applicant: IBM

    Inventor： LEBIZAY GERALD ,  MUNIER JEAN M ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR

    IPC: H04L12/56

    Abstract: The present invention relates to an efficient point-to-point and multi-points routing system and method for programmable data communication adapters in packetswitching nodes of high speed networks. The general principles of this efficiency are as follows. First, data packets are never copied, only packet pointers are copied for each destination, Space in Buffer Memory is saved, the number of instructions is significantly reduced improving the packet throughput (number of packets per seconds that the adapter is able to transmit). and the routing is independent of the packets length. Second, no overhead is generated by the multi-points mechanism in the real time procedures, the underrun/overrun problems on the outputs are reduced and the efficiency of the adapter in term data throughput (bits per second) is significantly improved. Third, each output is processed independently by means of interrupts, lines are managed in real time and lines of different speed or protocol can be supported in parallel. Fourth, the release of the resources is entirely realized on a non priority mode.

    16.
    发明专利
    未知

    公开(公告)号：BR9402596A

    公开(公告)日：1995-06-13

    申请号：BR9402596

    申请日：1994-06-29

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

    IPC: H04L29/06 ,  H04L12/56

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

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