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公开(公告)号：JPS63275241A
公开(公告)日：1988-11-11
申请号：JP5957588
申请日：1988-03-15
Applicant: IBM
Inventor： ROBBE JEAN-CLAUDE , MUNIER JEAN-MARIE , PORET MICHEL
IPC: G06F13/42
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公开(公告)号：DE3275692D1
公开(公告)日：1987-04-16
申请号：DE3275692
申请日：1982-12-28
Applicant: IBM , IBM FRANCE
Inventor： AMBOISE MODESTE , DEMANGE MICHEL , LEBIZAY GERARD , MUNIER JEAN-MARIE , PEYRONNENC MICHEL HENRI PAUL
Abstract: The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.
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公开(公告)号：DE3780306D1
公开(公告)日：1992-08-13
申请号：DE3780306
申请日：1987-04-22
Applicant: IBM
Inventor： AUSTRUY PIERRE , MUNIER JEAN-MARIE , PORET MICHEL
Abstract: A partitioned processing unit is used having two independent processing unit parts (26,28) and a partitioned switching device having two independent switch parts (38,40). Each switch part is associated logically with a corresp. part of the partitioned processing unit. Each processing unit part is connected to an associated group of adapters by a respective primary bus (52,54) and to the group of aoapters of the other unit by a respective secondary bus (46,48). A service processor (14) checks continuously the status of both processing unit parts and if either one fails it controls the bus-switching by operation of the switches (38,40) to maintain all the adaptors connected to whichever processing unit is still working.
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公开(公告)号：DE3480303D1
公开(公告)日：1989-11-30
申请号：DE3480303
申请日：1984-06-29
Applicant: IBM , IBM FRANCE
Inventor： BALLATORE DANIEL , HUON SIMON , MUNIER JEAN-MARIE
IPC: G06F13/368 , G06F13/378 , G06F13/36
Abstract: An arbitration device for enabling a common resource to be shared by a plurality of processors, all connected by a common bus and each processor having a certain access priority. When more than one processor requests access to the resource, the highest priority processor request signal is latched and access is granted while the other requesting processor's latches remain set (access not granted). If two processors request access while the resource is busy, then only the latch of the processor having the highest priority of the two will be reset when the bus becomes available, and that processor will gain access.
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公开(公告)号：AT78114T
公开(公告)日：1992-07-15
申请号：AT87430011
申请日：1987-04-22
Applicant: IBM
Inventor： AUSTRUY PIERRE , MUNIER JEAN-MARIE , PORET MICHEL
Abstract: A Control Unit is described, including a Processing Unit (12) controlled by a Service Processor (14), and a plurality of adapters (18) exchanging data and/or control signals with said Processing Unit (PU). For ensuring a continuous operation of the Control Unit, the adapters are partitioned into at least two sets (56,58), and the PU is partitioned into at least two parts (26,28), each set of adapters being connected to a dedicated PU part by a primary bus (52,54). Besides, in order to allow the fallback of a set of adapters onto another PU part if the PU part to which it is normally connected is inoperative, a bus switching device (30) is provided. This bus switching device includes at least two Switch parts (38,40), and each Switch part performs the switching of a given set of adapters onto a given PU part, according to the status of each PU part. Therefore, each Switch part is connected to a given set of adapters by a primary bus (52,54), and to the other sets of adapters by secondary busses (46,48) which become active in fallback mode.
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Patent Agency Ranking
公开(公告)号：DE69305734T2
公开(公告)日：1997-05-15
申请号：DE69305734
申请日：1993-06-30
Applicant: IBM
Inventor： GALAND CLAUDE , MAUDUIT DANIEL , PAUPORTE ANDRE , SPAGNOL VICTOR , LEBIZAY GERALD , MUNIER JEAN-MARIE , SAINT-GEORGES ERIC
IPC: H04L29/06
Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.
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公开(公告)号：DE69305734D1
公开(公告)日：1996-12-05
申请号：DE69305734
申请日：1993-06-30
Applicant: IBM
Inventor： GALAND CLAUDE , MAUDUIT DANIEL , PAUPORTE ANDRE , SPAGNOL VICTOR , LEBIZAY GERALD , MUNIER JEAN-MARIE , SAINT-GEORGES ERIC
IPC: H04L29/06
Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.
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公开(公告)号：BR9402596A
公开(公告)日：1995-06-13
申请号：BR9402596
申请日：1994-06-29
Applicant: IBM
Inventor： GALAND CLAUDE , LEBIZAY GERALD , MAUDUIT DANIEL , MUNIER JEAN-MARIE , PAUPORTE ANDRE , SAINT-GEORGES ERIC , SPAGNOL VICTOR
Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.
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公开(公告)号：AT144870T
公开(公告)日：1996-11-15
申请号：AT93480087
申请日：1993-06-30
Applicant: IBM
Inventor： GALAND CLAUDE , MAUDUIT DANIEL , PAUPORTE ANDRE , SPAGNOL VICTOR , LEBIZAY GERALD , MUNIER JEAN-MARIE , SAINT-GEORGES ERIC
IPC: H04L29/06
Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.
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公开(公告)号：DE68925696D1
公开(公告)日：1996-03-28
申请号：DE68925696
申请日：1989-12-22
Applicant: IBM
Inventor： MUNIER JEAN-MARIE , PAUPORTE ANDRE , POIRAUD CLEMENT
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