公开(公告)号：DE3374256D1

公开(公告)日：1987-12-03

申请号：DE3374256

申请日：1983-07-28

Applicant: IBM ,  IBM FRANCE

Inventor： HUON SIMON ,  SPAGNOL VICTOR

IPC: H04L29/10 ,  G06F5/06 ,  H04J3/16 ,  H04L13/08 ,  H04L25/05 ,  H04L29/02 ,  H04N5/217 ,  G06F13/00 ,  H04L25/36

Abstract: In a system where binary data from terminals operating at their own rates are multiplexed and selected asynchronously in gps. of bits, a random-access memory (66) comprises four rows with distinct addresses (EB1-EB4) and eight columns. Associated with the RAM (66) are input pointer registers (EBIN,PROCPTR) for rows and columns respectively and output line address registers (EBOUT). Control logic (72) indicates the sequence of memory addresses assigned to each active channel, for each selected configuration of input channels. Microinstructions are extracted from the logic (72,74) at a clock rate which is higher than the max. rate of arrival of binary data from any terminal.

公开(公告)号：DE3474394D1

公开(公告)日：1988-11-03

申请号：DE3474394

申请日：1984-06-29

Applicant: IBM ,  IBM FRANCE

Inventor： SPAGNOL VICTOR ,  HUON SIMON

IPC: G06F13/00 ,  H03K5/19 ,  H04L1/24 ,  H04L7/04 ,  H04L7/08 ,  H04L13/18 ,  H04L69/40

Abstract: The bit sequence is stored as a decision table in a memory (60), consulted at the address given by a counter (34) as each bit is received on the serial transmission line (12). If the bit found at that address coincides with the one received, the address counter is incremented and the next bit awaited. If the specified address is zero it is held at that value while another bit is awaited; and if not, the counter is reset to zero and the bit on the line is presented to the table again at the zero address. The complete sequence is detected when the count attains the number of bits sought and the last comparison is positive.

公开(公告)号：AT144870T

公开(公告)日：1996-11-15

申请号：AT93480087

申请日：1993-06-30

Applicant: IBM

Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

IPC: H04L29/06

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：CA2120558A1

公开(公告)日：1994-12-31

申请号：CA2120558

申请日：1994-04-05

Applicant: IBM

Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

IPC: H04L29/06 ,  H04L12/56

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：DE3586758T2

公开(公告)日：1993-04-22

申请号：DE3586758

申请日：1985-04-30

Applicant: IBM

Inventor： BELLOC JACQUES ,  CHOLAT-NAMY JEAN ,  CHOQUET MICHEL ,  HUON SIMON ,  PILOST DANIEL ,  SPAGNOL VICTOR ,  DE SAINT MICHEL FRANCOIS

IPC: H04L69/40 ,  H04L1/24 ,  H04L12/26

Abstract: A DTE can control the modems attached thereto by transmitting command messages over the data path and analyzing report messages supplied by the modems in return. Each command message is identified by a specific header. A command message intended for a remote modem (34) is intercepted by the local modem (30) and reformatted so as to obtain a supervisory message that is then transmitted at the rate of one bit per baud. A command message intended for a remote multichannel modem (48) is transmitted either by a supervisory message or in the data mode of operation.

公开(公告)号：DE3586758D1

公开(公告)日：1992-11-19

申请号：DE3586758

申请日：1985-04-30

Applicant: IBM

Inventor： BELLOC JACQUES ,  CHOLAT-NAMY JEAN ,  CHOQUET MICHEL ,  HUON SIMON ,  PILOST DANIEL ,  SPAGNOL VICTOR ,  DE SAINT MICHEL FRANCOIS

IPC: H04L69/40 ,  H04L1/24 ,  H04L12/26

Abstract: Data terminal equipment (10) sends commands identified by specific headers to the modems over a channel, and analyses the return messages. A command to a distant modem (34) is intercepted by the local modem (30) and its format is changed into a supervisory message with a different header, for transmission at the rate of 1 bit per baud. For a distant multichannel modem (48) the command is sent either by way of a supervisory message or in data mode. Second level modems (54,58) also may be monitored by addressed data-mode comands. commands.

公开(公告)号：DE69305734T2

公开(公告)日：1997-05-15

申请号：DE69305734

申请日：1993-06-30

Applicant: IBM

Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

IPC: H04L29/06

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：DE69305734D1

公开(公告)日：1996-12-05

申请号：DE69305734

申请日：1993-06-30

Applicant: IBM

Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

IPC: H04L29/06

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：CA2144402A1

公开(公告)日：1995-10-15

申请号：CA2144402

申请日：1995-03-10

Applicant: IBM

Inventor： LEBIZAY GERALD ,  MUNIER JEAN M ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR

IPC: H04L12/56

Abstract: The present invention relates to an efficient point-to-point and multi-points routing system and method for programmable data communication adapters in packetswitching nodes of high speed networks. The general principles of this efficiency are as follows. First, data packets are never copied, only packet pointers are copied for each destination, Space in Buffer Memory is saved, the number of instructions is significantly reduced improving the packet throughput (number of packets per seconds that the adapter is able to transmit). and the routing is independent of the packets length. Second, no overhead is generated by the multi-points mechanism in the real time procedures, the underrun/overrun problems on the outputs are reduced and the efficiency of the adapter in term data throughput (bits per second) is significantly improved. Third, each output is processed independently by means of interrupts, lines are managed in real time and lines of different speed or protocol can be supported in parallel. Fourth, the release of the resources is entirely realized on a non priority mode.

公开(公告)号：BR9402596A

公开(公告)日：1995-06-13

申请号：BR9402596

申请日：1994-06-29

Applicant: IBM

Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

IPC: H04L29/06 ,  H04L12/56

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.