公开(公告)号：PL1653365T3

公开(公告)日：2011-07-29

申请号：PL05108507

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F12/08

公开(公告)号：PL1653343T3

公开(公告)日：2011-03-31

申请号：PL05108510

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

公开(公告)号：AT449374T

公开(公告)日：2009-12-15

申请号：AT08150756

申请日：2004-05-06

Applicant: IBM

Inventor： HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH ,  SLEGEL TIMOTHY

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：ES2327058T3

公开(公告)日：2009-10-23

申请号：ES06116358

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08

Abstract: Un método para invalidar una gama de dos o más elementos de una tabla de traducción de direcciones en un sistema informático que tiene tablas de traducción de direcciones, dispuestas en tablas de segmentos y tablas de regiones, donde un elemento en una tabla de regiones corresponde a una tabla de segmentos, para traducir dinámicamente direcciones virtuales a direcciones de almacenamiento principal, el método comprende los pasos de: determinar la instrucción ejecutable desde un código de operación de una máquina para ser ejecutada, que la instrucción esté configurada para iniciar la ejecución de una operación de invalidación y borrado; y ejecutar la instrucción, comprendiendo el paso de ejecución las etapas de: interpretar la instrucción para identificar una rutina de software determinada para emular la operación de la instrucción en una unidad central de procesamiento subyacente que tiene una arquitectura de conjuntos de instrucciones diferente, la rutina de software predeterminada comprende una pluralidad de instrucciones; ejecutar la rutina de software predeterminada; invalidar (402, 404, 406) la gama de dos o más elementos de una tabla de traducción de direcciones; en la que la gama es especificada como una gama específica de elementos de una tabla de traducción de direcciones.

公开(公告)号：AT382896T

公开(公告)日：2008-01-15

申请号：AT04731399

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：DE112004000464T5

公开(公告)日：2006-06-01

申请号：DE112004000464

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：GB2413876A

公开(公告)日：2005-11-09

申请号：GB0516192

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

Abstract: Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

公开(公告)号：DE19848742C2

公开(公告)日：2002-05-02

申请号：DE19848742

申请日：1998-10-22

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/28

Abstract: A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.

公开(公告)号：CY1114228T1

公开(公告)日：2016-08-31

申请号：CY131100390

申请日：2013-05-16

Applicant: IBM

Inventor： GREINER DAN ,  GAINEY CHARLES JR ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN ,  SLEGEL TIMOTHY ,  WEBB CHARLES

IPC: G06F12/14 ,  G06F12/10

Abstract: Παρέχεταιμέσοβελτιωμένηςδυναμικήςμετάφρασηςδιευθύνσεων. Σεμιαυλοποίηση, αρχικάλαμβάνεταιμιαιδεατήδιεύθυνσηπουπρόκειταιναμεταφραστείκαιμιααρχικήδιεύθυνσηπροέλευσηςενόςπίνακαμετάφρασηςτηςιεραρχίαςτωνπινάκωνμετάφρασης. Βάσειτηςλαμβανόμενηςαρχικήςπροέλευσηςλαμβάνεταιμιακαταχώρησηπίνακατμημάτων. Ηκαταχώρησηπίνακατμημάτωνδιαμορφώνεταιώστεναπεριέχειπεδίοελέγχουμορφοτύπουκαιπεδίοεγκυρότηταςπρόσβασης. Εάνταπεδίαελέγχουμορφοτύπουκαιεγκυρότηταςπρόσβασηςείναιενεργοποιημένα, ηκαταχώρησηπίνακατμημάτωνπεριέχειεπίσηςπεδίοελέγχουπρόσβασης, πεδίοπροστασίαςαπόμετάκλησηκαιαπόλυτηδιεύθυνσηπλαισίουτμήματος. ΟιλειτουργίεςαποθήκευσηςεπιτρέπονταιμόνοεάντοπεδίοελέγχουπρόσβασηςταυτίζεταιμεκλειδίπρόσβασηςπρογράμματοςπουπαρέχεταιαπόΛέξηΚατάστασηςΠρογράμματοςή απότελεστήεντολήςπρογράμματοςπουεκτελείται. Οιλειτουργίεςμετάκλησηςεπιτρέπονταιεάντοκλειδίπρόσβασηςπρογράμματοςπουσυσχετίζεταιμετηνιδεατήδιεύθυνσηείναιίσομετοπεδίοελέγχουπρόσβασηςτμήματος.

公开(公告)号：ES2408189T3

公开(公告)日：2013-06-18

申请号：ES09700829

申请日：2009-01-05

Applicant: IBM

Inventor： GREINER DAN ,  GAINEY CHARLES JR ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN ,  SLEGEL TIMOTHY ,  WEBB CHARLES

IPC: G06F12/14 ,  G06F12/10

Abstract: Un método para proteger datos en un sistema de ordenador (100) que tiene una jerarquía de tablas de traducción(410, 412, 414, 416) utilizadas para la traducción de una dirección virtual a una dirección traducida de un bloque dedatos en almacenamiento principal, comprendiendo el método: obtener la dirección virtual que ha de ser traducida; obtener un origen inicial de una tabla de traducción de dicha jerarquía de tablas de traducción, comprendiendo dichajerarquía de tablas de traducción una tabla de segmento; basándose en el origen inicial obtenido, obtener una entrada de tabla de segmento a partir de dicha tabla desegmento, configurada dicha entradas de tabla de segmento para contener un campo de control de formato; en respuesta a una función de DAT mejorada que es habilitada, determinar si dicho campo de control de formato endicha entrada de tabla de segmento está habilitado; y en respuesta a dicho campo de control de formato que está habilitado, realizar: la determinación de si dicho campo de validez de acceso en dicha entrada de tabla de segmento está habilitado,comprendiendo dicha entrada de tabla de segmento dicho campo de validez de acceso, un campo de control deacceso de segmento, un campo de protección de búsqueda de segmento, y una dirección absoluta de trama desegmento de un gran bloque de datos deseado en el almacenamiento principal.