公开(公告)号：DE3382179D1

公开(公告)日：1991-04-04

申请号：DE3382179

申请日：1983-12-21

Applicant: IBM

Inventor： CARRUBBA FRANK PAUL ,  COCKE JOHN ,  KREITZER NORMAN ,  RADIN GEORGE

IPC: G06F12/08 ,  G06F12/12

Abstract: A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement with the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory. … The present cache architecture and control features render broadcasting between the data cache and instruction cache unnecessary. Moditication of the instruction cache is not permitted. Accordingly, control bits indicating a modification in the cache directory for the instruction cache are not necessary and similarly it is never necessary to store instruction cache lines back into main memory since their modification is not permitted. … The cache architecture and controls permit normal instruction and data cache fetches and data cache stores. Additionally, special instructions are provided for setting the special control bits provided in both the instruction and data cache directories, independently of actual memory accessing OPS by the CPU and for storing and loading cache lines independently of memory OPS by the CPU.

公开(公告)号：DE3483152D1

公开(公告)日：1990-10-11

申请号：DE3483152

申请日：1984-05-30

Applicant: IBM

Inventor： FISK DALE EDWARD ,  PEREIRA LAWRENCE WILLIAM ,  RADIN GEORGE

IPC: G06F7/00 ,  F02B75/02 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F13/36

Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.

公开(公告)号：CA1217869A

公开(公告)日：1987-02-10

申请号：CA469464

申请日：1984-12-06

Applicant: IBM

Inventor： FISK DALE E ,  PEREIRA LAWRENCE W ,  RADIN GEORGE

IPC: G06F7/00 ,  F02B75/02 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F13/36

Abstract: INTERNAL BUS ARCHITECTURE FOR A PRIMITIVE INSTRUCTION SET MACHINE An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture of the internal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were architected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.

公开(公告)号：DE3366762D1

公开(公告)日：1986-11-13

申请号：DE3366762

申请日：1983-10-21

Applicant: IBM

Inventor： FISK DALE EDWARD ,  GRIFFITH ROBERT LEROY ,  HOMAN MERLE EDWARD ,  RADIN GEORGE ,  RICHARDS WALDO

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455 ,  G06F9/44

Abstract: If a predetermined field (Figure 3/27) within a source instruction indexes and accesses a body of control information from memory (Figure 2/5), and if control information (Figure 4) designates the field-to-field (register-to-register) mapping (Figure 6), then a skeleton target instruction (Figure 3/29; Figure 4) can be filled in by either selectively copying the fields of the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instuctions for a CPU of a second kind without disrupting the logical flow or execution of either source ortarget instruction streams.

公开(公告)号：CA1199420A

公开(公告)日：1986-01-14

申请号：CA443643

申请日：1983-12-19

Applicant: IBM

Inventor： CARRUBBA FRANCIS P ,  COCKE JOHN ,  KREITZER NORMAN H ,  RADIN GEORGE

IPC: G06F12/08 ,  G06F12/12

Abstract: A HIERARCHICAL MEMORY SYSTEM INCLUDING SEPARATE CACHE MEMORIES FOR STORING DATA AND INSTRUCTIONS A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement within the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory.