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公开(公告)号：BR9000112A
公开(公告)日：1990-10-23
申请号：BR9000112
申请日：1990-01-12
Applicant: IBM
Inventor： GROHOSKI GREGORY FREDERICK , KAHLE JAMES ALLAN , NGUYENPHU MYHONG , RAY DAVID SCOTT
Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.
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公开(公告)号：MY122053A
公开(公告)日：2006-03-31
申请号：MYPI9804914
申请日：1998-10-28
Applicant: IBM
Inventor： TUNG SHIH-HSIUNG STEPHEN , RAY DAVID SCOTT , CHIAROT KEVIN ARTHUR , WILLIAMSON BARRY DUANE
Abstract: THE PRESENT INVENTION IS DIRECTED TOWARDS A MEANS TO DETECT AND REORDER OUT OF ORDER INSTRUCTIONS THAT MAY VIOLATE DATA COHERENCY. THE INVENTION COMPRISES A MIS-QUEUE TABLE (600) FOR HOLDING ENTRIES OF INSTRUCTION DATA, EACH ENTRY CORRESPONDING TO AN INSTRUCTION IN A COMPUTER MICROPROCESSOR (10). THE INSTRUCTION DATA IN EACH ENTRY COMPRISES: I) ADDRESS INFORMATION (510) FOR THE INSTRUCTION; II) ORDERING INFORMATION (570) FOR THE INSTRUCTION, INDICATING THE ORDER OF THE INSTRUCTION RELATIVE TO OTHER INSTRUCTIONS IN THE MIS-QUEUE TABLE; III) DATA MODIFICATION INFORMATION (530) FOR THE INSTRUCTION, FOR INDICATING A POSSIBILITY OF MODIFIED DATA; AND IV) OUT OF ORDER INFORMATION (520), FOR INDICATING THAT A NEWER INSTRUCTION HAS COMPLETED BEFORE THE CORRESPONDING OLDER INSTRUCTION TO THE ENTRY. THE INVENTION ALSO COMPRISES AN OUT OF ORDER COMPARATOR FOR COMPARING AN ADDRESS OF A COMPLETED INSTRUCTION TO ANY ADDRESS INFORMATION ENTRIES IN THE MISS QUEUE. IF A COMPLETED INSTRUCTION ACCESSES THE SAME ADDRESS AS ANOTHER INSTRUCTION, AS INDICATED IN THE ADDRESS INFORMATION IN THE MIS-QUEUE TABLE, AND THE COMPLETED INSTRUCTION IS NEWER THAN THE MATCHED INSTRUCTION, THE OUT OF ORDER FIELD IS MARKED INDICATING THIS CONDITION EXISTS. THE INVENTION COMPRISES A MODIFICATION COMPARATOR. THIS COMPARES ADDRESSES FROM DATA ALTERING EVENTS TO THOSE ADDRESSES IN THE ENTRIES IN THE MIS-QUEUE TABLE. ON A MATCH, THE MODIFICATION FIELD OF THE CORRESPONDING ENTRY IS MARKED TO INDICATE THIS CONDITION EXISTS. WHEN AN INSTRUCTION ENTRY INDICATES THAT THE CORRESPONDING INSTRUCTION''S DATA IS MODIFIED, AND THAT THE INSTRUCTION IS OUT OF ORDER, ALL SUBSEQUENT INSTRUCTIONS ARE CANCELED. (FIG. 8)
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公开(公告)号：DE69429226T2
公开(公告)日：2002-08-08
申请号：DE69429226
申请日：1994-09-15
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN JR
IPC: G06F9/38
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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公开(公告)号：ES2165375T3
公开(公告)日：2002-03-16
申请号：ES94306765
申请日：1994-09-15
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN HENRY STANLEY JR
IPC: G06F9/38
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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公开(公告)号：DE69429226D1
公开(公告)日：2002-01-10
申请号：DE69429226
申请日：1994-09-15
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN JR
IPC: G06F9/38
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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Patent Agency Ranking
公开(公告)号：CA2260308A1
公开(公告)日：1999-08-10
申请号：CA2260308
申请日：1999-01-25
Applicant: IBM
Inventor： WILLIAMSON BARRY DUANE , RAY DAVID SCOTT , TUNG SHIH-HSIUNG STEPHEN
Abstract: One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the first and final access into the order required by the load instruction; and storing the re-assembled data to the register file.
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公开(公告)号：DE68927911T2
公开(公告)日：1997-09-18
申请号：DE68927911
申请日：1989-12-20
Applicant: IBM
Inventor： GROHOSKI GREGORY FREDERICK , KAHLE JAMES ALLAN , NGUYENPHU MYHONG , RAY DAVID SCOTT
Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.
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公开(公告)号：DE68927911D1
公开(公告)日：1997-04-30
申请号：DE68927911
申请日：1989-12-20
Applicant: IBM
Inventor： GROHOSKI GREGORY FREDERICK , KAHLE JAMES ALLAN , NGUYENPHU MYHONG , RAY DAVID SCOTT
Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.
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公开(公告)号：BR9403516A
公开(公告)日：1995-06-20
申请号：BR9403516
申请日：1994-09-12
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN HENRY STANLEY JR
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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公开(公告)号：AU618142B2
公开(公告)日：1991-12-12
申请号：AU4433789
申请日：1989-11-02
Applicant: IBM
Inventor： GROHOSKI GREGORY FREDERICK , RAY DAVID SCOTT , NGUYENPHU MYHONG , KAHLE JAMES ALLAN
Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.
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