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    11.
    发明专利
    未知

    公开(公告)号：BR8903812A

    公开(公告)日：1990-03-20

    申请号：BR8903812

    申请日：1989-07-31

    Applicant: IBM

    Inventor： AKBAR SHAH ,  KROESEN PATRICIA LAVELLE ,  OGURA SEIKI ,  ROVEDO NIVO

    IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/70

    Abstract: A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer (12); a base layer (14) disposed over the collector layer; an emitter layer (16) disposed over the base layer; a first sidewall insulating layer (18) disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer (20) disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer (22) formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect (24) disposed on a surface of the base contact extension layer and; a collector contact extension layer (26) formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect (29) disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

    SIDEWALL SPACERS FOR CMOS CIRCUIT STRESS RELIEF/ISOLATION ANDMETHOD FOR MAKING
    12.
    发明专利
    SIDEWALL SPACERS FOR CMOS CIRCUIT STRESS RELIEF/ISOLATION ANDMETHOD FOR MAKING 未知

    公开(公告)号：AU579764B2

    公开(公告)日：1988-12-08

    申请号：AU6995987

    申请日：1987-03-12

    Applicant: IBM

    Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

    IPC: H01L21/76 ,  H01L21/762

    Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

    Method to engineer etch profiles in si substrate for advanced semiconductor devices
    13.
    发明专利
    Method to engineer etch profiles in si substrate for advanced semiconductor devices 未知

    公开(公告)号：SG129354A1

    公开(公告)日：2007-02-26

    申请号：SG200603915

    申请日：2006-06-08

    Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

    Inventor： FU CHONG YUNG ,  GREENE BRIAN JOSEPH ,  PANDA SIDDHARTHA ,  ROVEDO NIVO

    Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

    14.
    发明专利
    未知

    公开(公告)号：DE3784958D1

    公开(公告)日：1993-04-29

    申请号：DE3784958

    申请日：1987-01-23

    Applicant: IBM

    Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

    IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L21/225

    Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

    SIDEWALL SPACERS FOR CMOS CIRCUIT STRESS RELIEF/ISOLATION AND METHOD FOR MAKING
    16.
    发明专利
    SIDEWALL SPACERS FOR CMOS CIRCUIT STRESS RELIEF/ISOLATION AND METHOD FOR MAKING 未知

    公开(公告)号：CA1245373A

    公开(公告)日：1988-11-22

    申请号：CA529768

    申请日：1987-02-16

    Applicant: IBM

    Inventor： DALLY ANTHONY J ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

    IPC: H01L21/76 ,  H01L21/762 ,  H01L27/04

    Abstract: Sidewall Spacers For CMOS Circuit Stress Relief Isolation And Method For Making A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

    DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE
    17.
    发明专利
    DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE 未知

    公开(公告)号：SG132607A1

    公开(公告)日：2007-06-28

    申请号：SG2006077119

    申请日：2006-11-08

    Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD

    Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

    Abstract: A method for providing a dual stress memory technique in a semiconductor device (100) including an nFET (104, 204) and a pFET (106, 206) and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer (120) over the nFET (104) and a compressive stress layer (122) over the pFET (106), annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200 [err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

    20.
    发明专利
    未知

    公开(公告)号：DE68906095T2

    公开(公告)日：1993-10-28

    申请号：DE68906095

    申请日：1989-06-29

    Applicant: IBM

    Inventor： AKBAR SHAH ,  KROESEN PATRICIA LAVELLE ,  OGURA SEIKI ,  ROVEDO NIVO

    IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/72 ,  H01L29/52 ,  H01L29/60

    Abstract: A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer (12); a base layer (14) disposed over the collector layer; an emitter layer (16) disposed over the base layer; a first sidewall insulating layer (18) disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer (20) disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer (22) formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect (24) disposed on a surface of the base contact extension layer and; a collector contact extension layer (26) formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect (29) disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

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