公开(公告)号：JP2002319674A

公开(公告)日：2002-10-31

申请号：JP2002035743

申请日：2002-02-13

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  DALLY ANTHONY J ,  FIFIELD JOHN ATKINSON ,  HIGGINS JOHN JESSE ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM R ,  HEEL NICHOLAS MARTIN VAN

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor equipped having a dielectric layer of two-dimensional thickness, and to provide a method of manufacturing the same. SOLUTION: This manufacturing method comprises a first process of forming a mask with a through-hole 20 equipped with a side wall 21 on a structure (a), a second process of implanting suppression chemical seeds 24 into the structure through the through-hole 20 so as to form a suppression region 26 in the structure (b), and a third process of enabling a dielectric layer 28 to grow on the structure in the through-hole 20. Here, the suppression region 26 restrains the dielectric layer 28 partially from growing. By this setup, a self-aligned MOSFET or an anti-fuse device having a low overlap capacitance and a low gate induction drain leakage (i.e., low electric field) can be formed.

公开(公告)号：CA1245373A

公开(公告)日：1988-11-22

申请号：CA529768

申请日：1987-02-16

Applicant: IBM

Inventor： DALLY ANTHONY J ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/04

Abstract: Sidewall Spacers For CMOS Circuit Stress Relief Isolation And Method For Making A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：CA1244145A

公开(公告)日：1988-11-01

申请号：CA529470

申请日：1987-02-11

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  DALLY ANTHONY J ,  RISEMAN JACOB ,  OGURA SEIKI

IPC: H01L21/3205 ,  G03F7/09 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/72

Abstract: Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that o. the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photoresist sacrificial layer.