公开(公告)号：AU2002361847A1

公开(公告)日：2004-07-22

申请号：AU2002361847

申请日：2002-12-20

Applicant: IBM

Inventor： WANG LI-KONG ,  HSU LOUIS L ,  SHI LEATHEN

IPC: H01L21/336 ,  H01L21/86 ,  H01L27/12 ,  H01L29/786 ,  H01L23/14 ,  H01L29/12

公开(公告)号：DE60212962D1

公开(公告)日：2006-08-17

申请号：DE60212962

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HAO ,  HSU LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/27 ,  G01R31/3187 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.

公开(公告)号：DE60212962T2

公开(公告)日：2007-01-04

申请号：DE60212962

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HAO ,  HSU LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/27 ,  G01R31/3187 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.

公开(公告)号：ES2262810T3

公开(公告)日：2006-12-01

申请号：ES02732895

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HOWARD HAO ,  HSU LOUIS LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/27 ,  G01R31/3187 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

Abstract: Un aparato para proporcionar autocomprobación integrada jerárquica para un sistema con chip, comprendiendo dicho aparato: un controlador BIST central; una pluralidad de circuitos BIST locales comprendiendo cada uno al menos un macro y al menos un generador de imagen de prueba para generar imágenes de prueba predefinidas; y al menos un medio de comunicación para realizar operaciones de control y transferencia entre dicho controlador BIST central y dicha pluralidad de circuitos BIST locales, realizando dicho controlador BIST central la prueba de los circuitos BIST locales en una forma jerárquica siguiendo un algoritmo de prueba jerárquico.

公开(公告)号：AT332530T

公开(公告)日：2006-07-15

申请号：AT02732895

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HOWARD HAO ,  HSU LOUIS LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/22 ,  G06F11/27 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.