Abstract:
A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25% atomic using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same
Abstract:
PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation. SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present invention, a strained Si layer is formed on a semiconductor material, a second semiconductor layer, or both of them. According to the present invention, the strained Si layer has the same crystal orientation as either of a regrown semiconductor layer or the second semiconductor layer. This method provides the hybrid substrate wherein at least one of device layers contains the strained Si. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a method for fabricating a microwave circuit and a radio frequency circuit in a silicon on a sapphire substrate. SOLUTION: An improved method for fabricating a silicon on sapphire structure and/or device is disclosed. In one suitable embodiment, a single silicon oxide layer is interposed between a silicon layer and a sapphire layer by attaching the silicon oxide layer onto the silicon layer through growth or deposition and then attaching the sapphire layer to the oxide layer through wafer bonding. In another embodiment, a first silicon oxide layer is attached to the silicon layer through growth or deposition. Subsequently, a second silicon oxide layer is attached to the sapphire layer by deposition, for example. Thereafter, the first silicon oxide layer and the second silicon oxide layer are bonded by wafer bonding technology. COPYRIGHT: (C)2003,JPO
Abstract:
Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.
Abstract:
A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25% atomic using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same
Abstract:
PROBLEM TO BE SOLVED: To provide a method of manufacturing an SSOI structure which avoids epitaxial growth and subsequent wafer bonding steps. SOLUTION: A strained-semiconductor-on-insulator (SSOI) structure is manufactured. A strain-memorization technique is used to create strained semiconductor regions on an SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the semiconductor regions have been strained. The method disclosed includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the high stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polarity (tensile or compressive) of the stress can be controlled by the type and thickness of the high stress film. COPYRIGHT: (C)2008,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide an integrated circuit device which is formed on a SOI(silicon-on-insulator) substrate, which can realize highest performance of a specific device and has different crystal orientations. SOLUTION: The integrated circuit device includes at least the SOI substrate which has an upper semiconductor layer of a first crystal orientation and a semiconductor material of a second crystal orientation, the semiconductor material is substantially on the same plane surface and its thickness is the same to that of the upper semiconductor layer, and in an integrated circuit structure, the first crystal orientation is different from the second crystal orientation. The SOI substrate is formed by wafer bonding, ion implantation, and annealing. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a formation method for a heterostructure that can separate the fact that high strain is preferred in a strain Si layer and a Ge content in a low layer. SOLUTION: A first multilayered structure 10 of a strained Si layer 14 and tensile strain SiGe alloy layer 16 constitute on a relaxation SiGe alloy layer 12. Then, a second multilayered structure 18, including an insulating layer 20, is formed on a substrate 22 and jointed with the first multilayered structure 10. After the insulating layer 20 and the SiGe alloy layer 16 are jointed, the relaxing SiGe alloy layer 12 is completely removed. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a communication signal mixing/filtering system that employs a capsulated microelectric mechanical system(MEMS) device, and to provide its manufacturing method. SOLUTION: The microelectric mechanical system(MEMS) of a simple single structure combines a signal mixing step and a filtering step. The MEMS device is further reduced in size and made less expensive, and has higher reliability in its structure and operation as compared with those of the existing device adopting the conventional technology.
Abstract:
Communication signal mixing and filtering systems and methods utilizing an encapsulated micro electro-mechanical system (MEMS) device. Furthermore, disclosed is a method of fabricating a simple, unitarily constructed micro electro-mechanical system (MEMS) device which combines the steps of signal mixing and filtering, and which is smaller, less expensive and more reliable in construction and operation than existing devices currently employed in the technology.