公开(公告)号：GB1299113A

公开(公告)日：1972-12-06

申请号：GB1025470

申请日：1970-03-04

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: G11C11/411 ,  H01L27/00 ,  H01L27/07 ,  H01L27/102 ,  H03K3/286

Abstract: 1299113 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 4 March 1970 [11 March 1969] 10254/70 Heading H1K [Also in Divisions G4 and H3] In a matrix of bi-stable cells each (Fig. 1, not shown) has a pair of diodes (D1, D2) connecting its collector loads (R1, R0) to a respective pair of bit lines (B1, B0) which have resistors (R0) lower than R1, R2 acting as loads for the bistable when it is addressed. In integrated form, Figs. 3, 3A, each transistor has an N epitaxial layer forming the collector, an N+ emitter region contacted by the W line, and a P base region contacted by a connector B and extended to contact the V1 line, the resistor R1 or R2 being formed in this extended P region as a pinch resistor by a covering N+ diffusion. This diffusion also forms a connection to the collector region and is connected by a metal connector to the opposite base B. The diodes D1, D2 are formed in the epitaxial layer N. P + isolation zones are provided, and the layout is said to require a reduced number of isolation zones to carry all the components. The resistors R1, R2 may be formed alternatively as further, complementary, transistors.

公开(公告)号：GB1218896A

公开(公告)日：1971-01-13

申请号：GB2191269

申请日：1969-04-30

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: G11C11/411 ,  H01L27/07 ,  H03K3/286 ,  H03K3/288

Abstract: 1,218,896. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 30 April, 1969 [2 May, 1968], No. 21912/69. Heading H3T. [Also in Division H1] A bi-stable circuit such as a cross-coupled pair of transistors T1, T2 has a read/write circuit, comprising for example transistors T3, T4 receiving an address pulse at their commoned bases, reaction being effected by feeding extra current to the bi-stable, and writing by extracting current from the bi-stable. Thus, if T2 is ON, an address pulse (positive) at A causes transistor T4 to conduct and feed current into T2, its collector B1 potential consequently falling and turning OFF a transistor T8 of an emitter-coupled pair T7, T8 to give a positive output pulse. When writing, one transistor, say T6, of a write input pair T5, T6 is turned ON by a positive pulse at its base, thus causing the potential at T4 collector B1, to which T6 collector is coupled, to fall. If T2 is OFF, the emitter of T4 will be positive and this transistor will operate in reverse when a positive address pulse occurs at A. The current thus extracted at the junction 15 of collector resistors R21, R22 causes the point 15 and T2 collector C2 to fall to a certain extent, turning T1 OFF. The reciprocal coupling completes the changeover, and T2 comes ON. An integrated circuit form of construction is disclosed (Figs. 2, 3, not shown).

公开(公告)号：DE3269791D1

公开(公告)日：1986-04-17

申请号：DE3269791

申请日：1982-05-28

Applicant: IBM

Inventor： SOLOMON PAUL MICHAEL ,  WIEDMANN SIEGFRIED KURT

IPC: H03K17/60 ,  H03K19/00 ,  H03K19/013 ,  H03K19/088

公开(公告)号：DE3167300D1

公开(公告)日：1985-01-03

申请号：DE3167300

申请日：1981-07-06

Applicant: IBM

Inventor： REISMAN ARNOLD ,  SILVESTRI VICTOR JOSEPH ,  TANG DENNY DUAN-LEE ,  WIEDMANN SIEGFRIED KURT ,  YU HWA NIEN

IPC: H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8226 ,  H01L27/082 ,  H01L29/423 ,  H01L29/06 ,  H01L21/76 ,  H01L27/08

公开(公告)号：IT8021913D0

公开(公告)日：1980-05-09

申请号：IT2191380

申请日：1980-05-09

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: H03K17/66 ,  H03K19/013 ,  H03K19/082 ,  H03K

Abstract: Bipolar logic circuits such as inverters and NAND circuits are disclosed which are of extremely low DC power dissipation and very high speed. The basic circuit is an inverter circuit which incorporates at least a single switchable transistor (3). The emitter (6) of the NPN transistor (3) is connected to a potential level which may be ground while the collector is connected via a load device, a resistor or a complementary PNP transistor (2), to a positive power supply potential. The base (8) of the NPN transistor (3) is connected to a source (10) of standby current and via a parallel combination of a capacitor (14) and diode (12) to an input terminal (15). When the NPN transistor (3) is switched OFF by the application of a negatively going signal, standby current from the current source (10) is switched to ground via the diode (12) which has a lower switching point than the emitter-base diode of the NPN transistor. The capacitor (14) in parallel with the diode, is charged during this period so that when a positive going transient is applied at the input, the diode is backward-biased and the transient is applied along with the standby current to the base (8) of the NPN transistor, switching it to the conducting or ON state. … In addition to the basic logic circuit, a two-input NAND circuit which includes a pair of PNP bipolar transistors and a pair of NPN bipolar transistors disclosed.

公开(公告)号：GB1253763A

公开(公告)日：1971-11-17

申请号：GB6305969

申请日：1969-12-29

Applicant: IBM

Inventor： BERGER HORST HEINZ ,  WIEDMANN SIEGFRIED KURT ,  SCHUENEMANN CLAUS HEINRICH

IPC: G11C11/411 ,  G11C15/00 ,  H01L21/00 ,  H01L27/00 ,  H01L27/07 ,  H01L27/082 ,  H01L27/10 ,  H01L27/102 ,  H03K3/286 ,  H03K3/288 ,  H03K3/35

Abstract: 1,253,763. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINE CORP. 29 Dec., 1969 [30 Dec., 1968 (2); 31 Dec., 1968], No. 63059/69. Heading H3T. [Also in Divisions G4 and H1] A monolithic data storage cell has crosscoupled bipolar transistors T1, T2 with loads 10, 20 formed by controllable semi-conductor current sources, such as transistors of opposite type to T1, T2. The cell is selected by a pulse on a word line V2, and information is written in by lowering the emitter voltage of an appropriate one of a further pair of transistors T 3 , T 4 by means of bit lines B0, B1. Information is read out by a differential amplifier (not shown) detecting which of T3, T4 supplies the greater current upon selection of the cell (by V2). Alternatively, the cell may be selected by a positive pulse to the common emitter of 10, 20 (Fig. 12A, not shown) the bit lines being connected to the separate emitters of T1, T2, and the transistors T3, T4 being dispensed with. A further address signal may be applied to the commoned bases of 10, 20, enabling threedimensional matrix operation (Fig. 13A, not shown). The cross-coupled portion T1, T2 of Fig. 4 (Fig. 6A, not shown) and the remaining portion (Fig. 5A, not shown) are integrated (Figs. 6B, 6C and 5A, 5B, not shown) in separate portions of a monolith; and a matrix of the cells (Fig. 7, not shown) is described, the word line therein being in the co-called sub-collector and epitaxial layer of the isolated zone housing T1 and T2. The transistors T1, T2 are formed to operate inversely to the rest, so that space saving is achieved. The Fig. 4 circuit (also Fig. 8A, not shown) may be operated with V N and V 2 connected, and a more economical integrated layout used (Fig. 8B, not shown) for each cell, a matrix of which is described (Figs. 9A, 9B and 10, not shown). In Fig. 11 (not shown) a p + diffusion of low resistance replaces the metallized word line of Fig. 10 (not shown).

公开(公告)号：GB1208526A

公开(公告)日：1970-10-14

申请号：GB1897069

申请日：1969-04-14

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED KURT

IPC: G11C11/411 ,  H03K3/286 ,  H03K3/288

Abstract: 1,208,526. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 14 April, 1969 [13 April, 1968], No. 18970/69. Heading H3T. A cross-coupled bi-stable transistor pair T1, T2 deriving its emitter and collector supply potentials from a source 10, is switched in response to a pulse at B1, or B0 by raising the potential of the complete bi-stable (by a pulse from 10) relatively to a switching circuit, such as an emitter-coupled pair of transistors T3, T4. If T2 is OFF, and a " 1 " pulse is applied at B1, then when the pulse from 10 raises the potential V0 the base-emitter junction of T4 becomes forward biased and T4 conducts, the base current therein producing a potential drop across the collector resistor RC2 of T2 which is sufficient to turn off T1, and thus change the state of the bi-stable. Raising the potential of the bi-stable, instead of lowering the potential of the switching circuit transistors T3, T4 as happens in what is said to be the known circuit of Fig. 1 (not shown), enables the collector diodes (D0, D1) to be dispensed with. This facilitates integrated circuit construction, in which the collectors of the T3 transistors in a plurality of identical bi-stable stages are all formed in a common semi-conductor block; and similarly for the T4 collectors.