公开(公告)号：JP2003216306A

公开(公告)日：2003-07-31

申请号：JP2002017985

申请日：2002-01-28

Applicant: IBM

Inventor： CHU FRANK RUI-FENG ,  KAMIJO NOBORU ,  TANG DENNY DUAN-LEE

IPC: G06F3/02

Abstract: PROBLEM TO BE SOLVED: To provide a keyboard inputting device configured so as to be used satisfactorily like human engineering, and designed so that a relatively small area can be occupied. SOLUTION: A keyboard type inputting device is provided with a plurality of key positions provided as character input keys. Each key is made correspond to one key in the selected column of a conventional QWERTY array keyboard. A second set constituted of control keys is provided to select the column of the conventional QWERTY array keyboard expressed by character keys in addition to the other functions such as case shift and an alphanumeric control function. COPYRIGHT: (C)2003,JPO

公开(公告)号：DE3167300D1

公开(公告)日：1985-01-03

申请号：DE3167300

申请日：1981-07-06

Applicant: IBM

Inventor： REISMAN ARNOLD ,  SILVESTRI VICTOR JOSEPH ,  TANG DENNY DUAN-LEE ,  WIEDMANN SIEGFRIED KURT ,  YU HWA NIEN

IPC: H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8226 ,  H01L27/082 ,  H01L29/423 ,  H01L29/06 ,  H01L21/76 ,  H01L27/08

公开(公告)号：DE3381459D1

公开(公告)日：1990-05-17

申请号：DE3381459

申请日：1983-05-02

Applicant: IBM

Inventor： EPHRATH LINDA MERO ,  SILVESTRI VICTOR JOSEPH ,  TANG DENNY DUAN-LEE

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/74 ,  H01L21/763 ,  H01L21/205

公开(公告)号：SG65772A1

公开(公告)日：1999-06-22

申请号：SG1998001736

申请日：1998-07-07

Applicant: IBM

Inventor： BLAUM MARIO ,  TANG DENNY DUAN-LEE ,  YASHUDA TAKEO

IPC: H03M13/00 ,  H03M13/39 ,  H03M13/41 ,  H04J3/06 ,  H04L7/04 ,  H04L25/497 ,  H04L7/00

Abstract: A byte synchronization detection system and method in which a vector subtractor circuit determines an error vector between a current read data pattern and a synchronization bit pattern, and an offset adder circuit determines a Hamming Distance of the next read data pattern by adding the difference between the Hamming Distance from current error vector to the synchronization bit pattern and the Hamming Distance from the next error vector to the synchronization bit pattern. The Hamming Distance is determined by selected elements of the error vector which are the output from the vector subtractor circuit. The offset adder circuit determines a difference between the Hamming Distance of the current read data pattern and of the next read data pattern. The synchronization bit pattern is between 16 and 18 bits in length, inclusive. This approach reduces the probability of synchronization failure and/or mis-synchronization about 4 orders of magnitude over conventional approaches, while also reducing the length of the byte synchronization pattern to 16 bits.

公开(公告)号：DE3773663D1

公开(公告)日：1991-11-14

申请号：DE3773663

申请日：1987-12-18

Applicant: IBM

Inventor： CHAUNG CHING-TE KENT ,  HACKBARTH EDWARD ,  TANG DENNY DUAN-LEE

IPC: G11C11/41 ,  G11C11/411 ,  H01L21/8229 ,  H01L27/06 ,  H01L27/10 ,  H01L27/102

Abstract: This invention relates generally to Static Random Access Memories (SRAM) and more particularly, relates to a SRAM cell (1) wherein soft-error due to alpha -particle radiation is reduced by permitting the potential at the common-emitter node (11; 12) of the cross-coupled transistors (5; 6) of the memory cell to swing freely. Still more particularly, it relates to a SRAM cell wherein the common-emitter node of the cell is decoupled from a heavily capacitively loaded word line (3) with its common constant current source (21) by means of a constant current source (22) or current mirror disposed in each cell between the common-emitter node and the word line

公开(公告)号：DE3064247D1

公开(公告)日：1983-08-25

申请号：DE3064247

申请日：1980-06-24

Applicant: IBM

Inventor： FETH GEORGE CLARENCE ,  NING TAK HUNG ,  TANG DENNY DUAN-LEE ,  WIEDMANN SIEGFRIED KURT ,  YU HWA NIEN

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L21/82

Abstract: Self-aligned semiconductor circuits and process for manufacturing the circuits in which a plurality of transistors (206, 208, 240; 206, 208, 242) is provided, the collector regions/contacts (240, 228; 242, 228) and the base regions/contacts (254, 252; 256, 252) being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors (240, 242) of these transistors can be butted to a recessed field oxide (214) to reduce the extrinsic base area and to minimize excess charge storage in the base region (208). The base contacts, whether polysilicon or metal, etc., provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow.