公开(公告)号：DE60215513D1

公开(公告)日：2006-11-30

申请号：DE60215513

申请日：2002-08-06

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DOBUZINSKY MARK ,  KHAN ALI ,  LIU C ,  WENSLEY PAUL ,  YU CHIENFAN

IPC: H01L21/8242 ,  H01L21/3213 ,  H01L21/60 ,  H01L21/8234

Abstract: A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

公开(公告)号：DE102004016705A1

公开(公告)日：2004-11-25

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：SG46459A1

公开(公告)日：1998-02-20

申请号：SG1996004874

申请日：1993-10-05

Applicant: IBM

Inventor： JENG SWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

IPC: H01L21/00 ,  H01L21/302 ,  C23F4/00 ,  H01L21/3065 ,  H01L21/311

Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.