Multiple width features in integrated circuits

    公开(公告)号:GB2487309B

    公开(公告)日:2014-03-19

    申请号:GB201201714

    申请日:2010-10-19

    Applicant: IBM

    Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

    Verfahren und Struktur zum Bilden von Finfets mit mehreren Dotierungsbereichen auf demselben Chip

    公开(公告)号:DE112010004804T5

    公开(公告)日:2012-11-15

    申请号:DE112010004804

    申请日:2010-10-28

    Applicant: IBM

    Abstract: Ein Verfahren zum Herstellen von Elementen für eineiner ersten Halbleiterstruktur auf einer Fläche einer Halbleitereinheit und das epitaxiale Anwachsen von Halbleitermaterial auf gegenüber liegenden Seiten der ersten Halbleiterstruktur, um Finnen zu bilden. Auf einer Seite der ersten Halbleiterstruktur wird eine erste abgewinkelte Ionenimplantation angewendet, um eine entsprechende Finne auf der einen Seite zu dotieren. Die erste Halbleiterstruktur wird selektiv entfernt, um die Finnen frei zu legen. Unter Verwendung der Finnen werden Finnen-Feldeffekttransistoren gebildet.

    Method and structure for forming finfets with multiple doping regions on a same chip

    公开(公告)号:GB2488642A

    公开(公告)日:2012-09-05

    申请号:GB201202927

    申请日:2010-10-28

    Applicant: IBM

    Abstract: A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins.

    Multiple width features in integrated circuits

    公开(公告)号:GB2487309A

    公开(公告)日:2012-07-18

    申请号:GB201201714

    申请日:2010-10-19

    Applicant: IBM

    Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

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