公开(公告)号：JP2005175481A

公开(公告)日：2005-06-30

申请号：JP2004353555

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHANG YING ,  DORIS BRUCE B ,  KANARSKY THOMAS SAFRON ,  LEONG MEIKEI ,  KEDZIERSKI JAKUB TADEUSZ

IPC: H01L29/812 ,  H01L21/335 ,  H01L21/336 ,  H01L21/338 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To manufacture a high performance processor by achieving device width control in a FinFET device so as to provide a field effect device which performs high current drive in a given layout area.
SOLUTION: A field effect device, which has a body made of a crystalline semiconductor material and comprises at least one vertically oriented unit 11 and at least one horizontally oriented unit 12, is produced in an SOI layer through several etching steps. By providing a gate electrode 50, the segmented (unit type) field effect device can combine a FinFET type device, or a fully depleted silicon-on-insulator FET type device, and a fully depleted planar device.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过在FinFET器件中实现器件宽度控制来制造高性能处理器，以便提供在给定布局区域中执行高电流驱动的场效应器件。 解决方案：具有由晶体半导体材料制成的主体并且包括至少一个垂直取向单元11和至少一个水平取向单元12的场效应器件通过几个蚀刻步骤在SOI层中产生。 通过提供栅电极50，分段（单元型）场效应器件可以组合FinFET型器件或完全耗尽的绝缘体上硅FET器件和完全耗尽的平面器件。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：EP2145349A4

公开(公告)日：2012-03-28

申请号：EP08754077

申请日：2008-04-08

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  HENSON WILLIAM K ,  YAN HONGWEN ,  ZHANG YING

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

CPC classification number: H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

公开(公告)号：JP2005197734A

公开(公告)日：2005-07-21

申请号：JP2005000206

申请日：2005-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEVEN W ,  DORIS BRUCE B ,  ZHANG YING ,  ZHU HUILONG

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device, realizing a strained Si film with reduced number of defects.
SOLUTION: The strained Si film is formed by selectively growing a fin arranged in a perpendicular direction to the surface of a non-conductive substrate or Si on the side face of a relaxed SiGe block. Next, a dielectric gate comprising an oxide or a high k material or a combination thereof, for example, can be formed on the surface of the strained Si film. Further, by removing the relaxed SiGe block without substantially influencing the stress of the strained Si film, a second gate oxide can be formed on the surface previously occupied by the relaxed SiGe block. Thus, a MOSFET and a finFET of a single gate, double gate, or more gates can be formed, with the semiconductor device having the strained Si fin arranged in the perpendicular direction on the non-conductive substrate, with a channel having reduced number of defects or reduced dimension or both.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种方法和装置，实现了具有减少的缺陷数量的应变Si膜。 解决方案：通过选择性地生长沿垂直于非导电衬底的表面布置的翅片或在弛豫的SiGe块的侧面上的Si来形成应变Si膜。 接下来，可以在应变Si膜的表面上形成例如包含氧化物或高k材料或其组合的电介质栅。 此外，通过去除弛豫的SiGe块而基本上不影响应变的Si膜的应力，可以在松弛的SiGe块以前占据的表面上形成第二栅极氧化物。 因此，可以形成单栅极，双栅极或更多栅极的MOSFET和finFET，其中半导体器件具有沿非垂直方向布置在非导电衬底上的应变Si鳍，沟道具有减少的数量 缺陷或尺寸减小或两者兼有。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2007184584A

公开(公告)日：2007-07-19

申请号：JP2006343832

申请日：2006-12-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN TZE-CHIANG ,  DORIS BRUCE B ,  VAMSI K PARUCHURI ,  MICHAEL PATRIK CHUDZIK ,  VIJAY NARAYANAN ,  MICHELLE L STEEN ,  ALESSANDRO CALLEGARI ,  KIM YOUNG-HEE ,  ZHANG YING

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823857 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To prevent the depletion of the gate polysilicon of a CMOS by a gate electrode structure composed of a metal dielectric stack containing a large volume of potassium. SOLUTION: A semiconductor structure is provided by including an n-FET device and a p-FET device. At least either of the devices includes a gate electrode stack having a thin film of a silicon-containing electrode, i.e., polysilicon electrode and a first metal on the silicon-containing electrode. The other of the devices includes a gate electrode stack not having a thin film of a silicon-containing electrode but at least having a first metal gate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过由含有大量钾的金属电介质堆叠构成的栅电极结构来防止CMOS的栅极多晶硅的耗尽。 解决方案：通过包括n-FET器件和p-FET器件来提供半导体结构。 所述器件中的至少一个包括具有含硅电极的薄膜的栅电极堆叠，即多晶硅电极和含硅电极上的第一金属。 另一个器件包括不具有含硅电极薄膜但至少具有第一金属栅极的栅极电极堆叠。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002353246A

公开(公告)日：2002-12-06

申请号：JP2002110367

申请日：2002-04-12

Applicant: IBM

Inventor： CYRILLE CABRAL JR ,  KEVIN K CHAN ,  COHEN GUY MOSHE ,  GUARINI KATHRYN WILDER ,  LAVOIE CHRISTIAN ,  PAUL MICHAEL SOLOMON ,  ZHANG YING

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned silicide process applicable to contacting silicon, sidewall, source, and drain. SOLUTION: A method (and a structure formed by using this method) to form a metal silicide contact on a non-planar silicon-containing area which limits the silicon consumption at a silicon-containing area includes: forming a blanket metal layer over the silicon-containing area, forming a silicon layer over the metal layer, performing an selective and anisotropical etching of the silicon layer against the metal, forming a metal silicon alloy by reacting the metal and silicon at a first temperature, etching away any unreacted metal layer, forming a metal-Si2 alloy by annealing at a second temperature, and selectively etching away any unreacted silicon layer.

公开(公告)号：EP1680804A4

公开(公告)日：2008-07-09

申请号：EP04810466

申请日：2004-11-05

Applicant: IBM

Inventor： STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate (200) and forming a gap (219) in the semiconductor substrate (200) by removing at least a portion of the doped portion of the semiconductor substrate (200). The method further involves growing a strain layer (227) in at least a portion of the gap (219) in the semiconductor substrate (200). For the n-type device, the strain layer (227) is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

公开(公告)号：WO2005045901A3

公开(公告)日：2006-08-17

申请号：PCT/US2004037049

申请日：2004-11-05

Applicant: IBM ,  STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

Inventor： STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate (200) and forming a gap (219) in the semiconductor substrate (200) by removing at least a portion of the doped portion of the semiconductor substrate (200). The method further involves growing a strain layer (227) in at least a portion of the gap (219) in the semiconductor substrate (200). For the n-type device, the strain layer (227) is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Abstract translation: 一种制造包括n型器件和p型器件的器件的方法。 在本发明的一个方面，该方法包括通过去除半导体衬底（200）的掺杂部分的至少一部分来掺杂半导体衬底（200）的一部分并在半导体衬底（200）中形成间隙（219） ）。 该方法还包括在半导体衬底（200）中的间隙（219）的至少一部分中生长应变层（227）。 对于n型器件，应变层（227）在基本上直接位于n型器件的沟道下方的至少一部分上生长。 对于p型器件，应变层生长在基本上直接位于p型器件的源极区域或漏极区域的部分上，并且基本上不在p型器件的沟道下生长。

公开(公告)号：WO0247144A3

公开(公告)日：2003-02-13

申请号：PCT/US0145195

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHEN BOMY A ,  HIRSCH ALEXANDER ,  IYER SUNDAR K ,  ROVEDO NIVO ,  WANN HSING-JEN ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/7621 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/823481

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract translation: 在源极和漏极之下形成图案化的掩埋绝缘体，通过在身体区域上形成掩模并在要形成源极和漏极的区域中注入一定量的n或p型离子，然后蚀刻STI并蚀刻出植入 区。 光氧化之后是STI中的共形氧化物沉积以及蚀刻区域，从而仅在需要时形成掩埋氧化物。

公开(公告)号：WO2005045901A8

公开(公告)日：2006-02-02

申请号：PCT/US2004037049

申请日：2004-11-05

Applicant: IBM ,  STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

Inventor： STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L

CPC classification number: H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Abstract translation: 一种制造包括n型器件和p型器件的器件的方法。 在本发明的一个方面，该方法包括通过去除半导体衬底的掺杂部分的至少一部分来掺杂半导体衬底的一部分并在半导体衬底中形成间隙。 该方法还包括在半导体衬底中的间隙的至少一部分中生长应变层。 对于n型器件，应变层在基本上直接位于n型器件的沟道下方的至少一部分上生长。 对于p型器件，应变层生长在基本上直接位于p型器件的源极区域或漏极区域的部分上，并且基本上不在p型器件的沟道下生长。

公开(公告)号：GB2497399A

公开(公告)日：2013-06-12

申请号：GB201221060

申请日：2012-11-23

Applicant: IBM

Inventor： ZHANG YING ,  LIU FEI ,  GUILLORN MICHAEL

IPC: B81C1/00

Abstract: A hafnium oxide hard mask layer is used to define an opening for removing sacrificial silicon oxide material surrounding the electromechanical actuator 38A. The hafnium oxide hard mask layer is compatible with the use of HF vapour for removing the sacrificial oxide and releasing the electromechanical actuating member 38A with reduced stiction. The hafnium oxide hard mask is also formed over adjacent CMOS transistor circuitry during the release etching of the MEMS or NEMS switches