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    SHIELDED INTERCONNECTION FOR INTEGRATED CIRCUIT DEVICE
    12.
    发明专利
    SHIELDED INTERCONNECTION FOR INTEGRATED CIRCUIT DEVICE 失效

    公开(公告)号：JP2001308184A

    公开(公告)日：2001-11-02

    申请号：JP2001070270

    申请日：2001-03-13

    Applicant: IBM

    Inventor： JONATHAN D CHAPPURUSOKORU ,  IVERS THOMAS H ,  MCGAHAY VINCENT J ,  STAMPER ANTHONY K

    IPC: H01L23/522 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

    Abstract: PROBLEM TO BE SOLVED: To provide a shielded interconnection for reducing capacitive coupling between interconnecting lines in an integrated circuit device having interconnecting lines isolated by an interlayer dielectric. SOLUTION: Interconnecting lines are provided with a thin side wall conductive shield isolated from interconnecting lines by a thin side wall dielectric. Crosstalk between adjacent lines in an interconnection layer is reduced by a side wall shield. The thin side wall dielectric material can be selected to reduce capacitance between the side wall shield and the interconnecting lines. An interlayer dielectric can be selected to enhance defect resistance and mechanical strength during fabrication of a device. A method for fabricating shielded interconnections is also provided.

    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    14.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    在混合方向晶体管中对充电损害的保护

    公开(公告)号：WO2007115146B1

    公开(公告)日：2008-06-05

    申请号：PCT/US2007065604

    申请日：2007-03-30

    Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    IPC: H02H9/00

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下面的体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）通过埋入介质层（16）设置在与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

    Dual damascene wiring and its forming method
    15.
    发明专利
    Dual damascene wiring and its forming method 有权
    双面接线及其成型方法

    公开(公告)号：JP2006054433A

    公开(公告)日：2006-02-23

    申请号：JP2005183686

    申请日：2005-06-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MCDEVITT THOMAS L ,  STAMPER ANTHONY K

    IPC: H01L21/768 ,  H01L21/822 ,  H01L27/04

    CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/76808 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a new dual damascene wiring structure that improves the efficiency of dual damascene wiring by improving a dual damascene wiring formation method. SOLUTION: This method concerns the formation of a dual damascene interconnection structure and a related structure. In this formation, the related structure includes a dual damascene wiring in a dielectric substance layer. The above dual damascene wiring is extended into the dielectric substance layer at a distance shorter than the thickness of the corresponding dielectric substance layer, and a dual damascene via bar is integrated with the bottom of the dual damascene wiring and is extended toward the bottom of the dielectric substance later from that bottom. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种新的双镶嵌布线结构，通过改进双镶嵌布线形成方法来提高双镶嵌布线的效率。

    解决方案：该方法涉及形成双镶嵌互连结构和相关结构。 在该结构中，相关结构包括电介质层中的双镶嵌布线。 上述双镶嵌布线以比对应的电介质层的厚度短的距离延伸到电介质层中，并且双镶嵌通孔条与双镶嵌布线的底部一体化并且朝向底部延伸 电介质物质晚于该底部。 版权所有（C）2006，JPO＆NCIPI

    CAPACITOR DEVICE AND METHOD OF FORMING CAPACITOR
    17.
    发明专利
    CAPACITOR DEVICE AND METHOD OF FORMING CAPACITOR 审中-公开

    公开(公告)号：JP2002313939A

    公开(公告)日：2002-10-25

    申请号：JP2002060480

    申请日：2002-03-06

    Applicant: IBM

    Inventor： STAMPER ANTHONY K

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/334 ,  H01L21/768 ,  H01L21/822 ,  H01L27/08

    Abstract: PROBLEM TO BE SOLVED: To provide a more reliable damascene capacitor structure by preventing the occurrence of leakage and dielectric breakdown between capacitor plates. SOLUTION: A capacitor device is provided with a trench which is formed into an inter-level dielectric insulator layer and has sidewalls, a first thin lower conductor plate 32 formed on the bottom of the trench, and a second upper conductor plate 44 having a surface which is commonly formed as the surface of the dielectric insulator layer also. The capacitor device is also provided with a dielectric layer 42 formed between the conductor plates 32 and 44. The dielectric layer 42 prevents one of the conductor plates 32 and 44 from extending to the sidewalls of the trench and at least one upper corner of the conductor plate from extending toward the upper part of the trench.

    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION
    18.
    发明申请
    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 审中-公开
    通过光刻对齐和注册来实现硅通孔

    公开(公告)号：WO2011090852A2

    公开(公告)日：2011-07-28

    申请号：PCT/US2011020913

    申请日：2011-01-12

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Abstract translation: 制造集成电路结构的方法在衬底（100;图1）中形成第一开口并用保护性衬垫排列第一开口。 （102）该方法将材料沉积到第一开口（104）中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 （108）该方法通过保护材料中的第二开口从第一开口移除材料。 （110）过程控制标记包括保护材料内的凹部，其仅部分地延伸穿过保护材料，使得过程控制标记下方的部分基板不受移除材料的过程的影响。

    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES
    19.
    发明申请
    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES 审中-公开
    消除高反射性界面的CMOS图像

    公开(公告)号：WO2006071540A3

    公开(公告)日：2007-04-12

    申请号：PCT/US2005045328

    申请日：2005-12-14

    Applicant: IBM ,  ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

    Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

    IPC: H01L29/04

    CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

    Abstract translation: 一种图像传感器（20）及其制造方法，其中传感器包括铜（Cu）金属化水平（135a，135b），允许结合更薄的层间电介质堆叠（130a-130c）以产生呈现增加的像素阵列（100） 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属（132a，132b）的最小厚度的结构，或者具有从每个的光路中选择性地去除的阻挡层金属的部分（50） 像素，从而最小化反射率。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层（142）可以通过自对准沉积形成在Cu金属化之上。

    Bipolar transistor structure and manufacturing method therefor
    20.
    发明专利
    Bipolar transistor structure and manufacturing method therefor 有权
    双极晶体管结构及其制造方法

    公开(公告)号：JP2011003907A

    公开(公告)日：2011-01-06

    申请号：JP2010141326

    申请日：2010-06-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： STAMPER ANTHONY K ,  DAHLSTROM MATTIAS ERIK ,  BENOIT JOHN JOSEPH ,  GRAY PETER BRIAN ,  DUPUIS MARK DAVID

    IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

    CPC classification number: H01L29/732 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L29/34 ,  H01L29/66272

    Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor structure with enhanced performance by optimizing junction interface characteristics between an emitter and a base, and a manufacturing method therefor.SOLUTION: The bipolar transistor includes: (1) a collector region 15 located at least in-part within a semiconductor substrate; (2) a base region 16 contacting the collector region; and (3) an emitter region 24 contacting the base region. A damaged region 16A that includes an oxygen impurity and at least one impurity selected from a group consisting of a fluorine impurity and a carbon impurity is formed in a layer 16 that includes a base of an emitter aperture at an interface between the emitter region and the base region, thus the performance of the bipolar transistor being enhanced. The impurities may be introduced into the interface by plasma etch treatment or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material composing the base region.

    Abstract translation: 要解决的问题：通过优化发射极和基极之间的结界面特性来提供具有增强性能的双极晶体管结构及其制造方法。解决方案：双极晶体管包括：（1）至少位于 在半导体衬底内; （2）与收集器区域接触的基极区域16; 和（3）与基极区域接触的发射极区域24。 包含氧杂质和选自氟杂质和碳杂质的至少一种杂质的受损区域16A形成在层16中，该层16包括在发射极区域和发射极区域之间的界面处的发射极孔径的基极 从而提高了双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或替代地进行后处理，然后进行无水氨和氟化氢处理，构成基区的基材。

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