公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2001313296A

公开(公告)日：2001-11-09

申请号：JP2001081508

申请日：2001-03-21

Applicant: IBM

Inventor： MCGAHAY VINCENT J ,  ERNEST N LEVIN

IPC: H01L21/3205 ,  H01L21/283 ,  H01L21/316 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a barrier layer very effective for preventing diffusion of water and/or oxygen which is easily and reliably manufactured in an integrated circuit device including a copper structure. SOLUTION: In an integrated circuit, a diffusion barrier layer 18 made of a high density material for protecting a copper structure 40 from oxidation in the presence of oxygen or water being apt to bring about defects such as pin-holes is modified on site by oxidation of a material self-restrictively capable of making a protective oxide. This material is provided in contact with the high-density material preferably as a film 26. The protection for the copper structure 40 allows a high-conductivity copper to be used, combined with a known low-dielectric constant (low-k) material resistive to diffusion of oxygen and water.

公开(公告)号：JP2001024060A

公开(公告)日：2001-01-26

申请号：JP2000139087

申请日：2000-05-11

Applicant: IBM

Inventor： ROBERT COOK ,  GRECO STEPHEN E ,  JOHN P HUMMEL ,  JOYCE RYUU ,  MCGAHAY VINCENT J ,  REBECCA MEE ,  SRIVASTAVA KAMALESH

IPC: G03F7/40 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent invasion with a developer of SSQ dielectric material during the resist pattern formation by forming another resist pattern on the surface of an intermediate material, and then removing a part of the intermediate material and the other part of such material depending on the other resist pattern. SOLUTION: An etching process is executed to form an aperture 22' to a thin oxide layer 16 as an intermediate material depending on a pattern 20 generated in the resist 18 and also to form a recess 22 to the SSQ (silsesquioxane material) layer 14. The other resist layer 24 is coated on the surface of the oxide layer 16. This resist layer 24 is then exposed and developed to form a resist pattern 26. Moreover, depending on the pattern 26, it is then developed to generate an undercut 28' of a via resist 24. Thereafter, the via 27 is formed with the unisotropic etching process. As a result, while the resist pattern 26 is formed, the pattern is never invaded with the developer owing to the SSQ material.

公开(公告)号：JP2004228569A

公开(公告)日：2004-08-12

申请号：JP2004003456

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COONEY III EDWARD C ,  ROBERT M JEFFKEN ,  MCGAHAY VINCENT J ,  MOTSIFF WILLIAM T ,  MURRAY MARK P ,  PIPER AMANDA L ,  STAMPER ANTHONY K ,  THOMAS DAVID C ,  TYBERG CHRISTY S ,  WEBSTER ELIZABETH T

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76892 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide re-work processing methods of both the level of a single chip connecting or an interconnecting metal and a multilevel. SOLUTION: The method of re-working a BEOL (a back end of a process line) metallization levels of damascene metallurgy comprises the processes of: forming a plurality of BEOL metallization levels 101, 102 on a substrate 110; forming line and via portions in the BEOL metallization level; exposing the line section and the via section by selectively removing at least one BEOL metallization level; and replacing a removed BEOL metallization level with at least one of new BEOL metallization levels. The BEOL metallization levels 101, 102 comprises a first dielectric layers 120, 130 and second dielectric layers 125, 135, and the first dielectric layer includes a material having a dielectric constant lower than that of the second dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供单芯片连接或互连金属和多层的水平的再加工处理方法。 解决方案：重新加工大马士革冶金的BEOL（工艺线的后端）金属化水平的方法包括以下过程：在衬底110上形成多个BEOL金属化水平101,102; 在BEOL金属化水平上形成线和通孔部分; 通过选择性地去除至少一个BEOL金属化水平来暴露线段和通路部分; 并用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平。 BEOL金属化层101,102包括第一电介质层120,130和第二电介质层125,135，并且第一电介质层包括介电常数低于第二电介质层的介电常数的材料。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004214626A

公开(公告)日：2004-07-29

申请号：JP2003396313

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WILLIAM F LANDERS ,  SHAW THOMAS M ,  LLERA-HURLBURT DIANA ,  CROWDER SCOTT W ,  MCGAHAY VINCENT J ,  MALHOTRA SANDRA G ,  DAVIS CHARLES R ,  RONALD D GOLDBLATT ,  ENGEL BRETT H

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04

CPC classification number: H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To obtain improved crack stopping and contaminant barriers for an IC chip. SOLUTION: On-chip overlapped crack end barrier structure is constituted. A conductive material in barrier structure design is used for forming the depth of several conductive layers, by wiring each barrier to a contact pad and a device pin and connecting a monitoring device to a chip. Upper surface deposit, consisting of a material such as polyimide, suppresses peeling off of layers. Other barriers may include structural characteristics for completely shielding moisture absorption and oxidation, as compared with typical crack stopping structure. Thereto, other barriers are constituted so as to give crack stop protection, to be electrically connected to a monitoring device and so as to test the capacitance/resistance of the barrier structure to show the complete states of the barriers to a user. A barrier destroyed by cracks or humidity absorption/oxidation shows deviation in the capacitance/resistance. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004193605A

公开(公告)日：2004-07-08

申请号：JP2003405153

申请日：2003-12-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DALTON TIMOTHY J ,  DAS SANJIT K ,  ENGEL BRETT H ,  HERBST BRIAN W ,  HICHRI HABIB ,  KASTENMEIER BERND E ,  MALONE KELLY ,  MARINO JEFFREY R ,  MARTIN ARTHUR ,  MCGAHAY VINCENT J ,  MELVILLE IAN D ,  NARAYAN CHANDRASEKHAR ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for reducing thermal mechanical stress in stack and via. SOLUTION: An interconnection structure for a semiconductor device comprises an organic low-k (low specific dielectric constant) dielectric layer formed on a lower metallization. The via to be formed here is in this low-k dielectric layer, and combines a lower metallization line formed on the lower metallization level and an upper metallization line formed on an upper metallization level. This via is surrounded by structure collar selected from material with CTE that can protect the via from shearing force generated after the thermal expansion of the low-k dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2001308184A

公开(公告)日：2001-11-02

申请号：JP2001070270

申请日：2001-03-13

Applicant: IBM

Inventor： JONATHAN D CHAPPURUSOKORU ,  IVERS THOMAS H ,  MCGAHAY VINCENT J ,  STAMPER ANTHONY K

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a shielded interconnection for reducing capacitive coupling between interconnecting lines in an integrated circuit device having interconnecting lines isolated by an interlayer dielectric. SOLUTION: Interconnecting lines are provided with a thin side wall conductive shield isolated from interconnecting lines by a thin side wall dielectric. Crosstalk between adjacent lines in an interconnection layer is reduced by a side wall shield. The thin side wall dielectric material can be selected to reduce capacitance between the side wall shield and the interconnecting lines. An interlayer dielectric can be selected to enhance defect resistance and mechanical strength during fabrication of a device. A method for fabricating shielded interconnections is also provided.

公开(公告)号：JP2001267325A

公开(公告)日：2001-09-28

申请号：JP2001031135

申请日：2001-02-07

Applicant: IBM

Inventor： NYE III HENRY A ,  MCGAHAY VINCENT J ,  TALLMAN KURT A

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/77 ,  H01L23/00 ,  H01L23/58

Abstract: PROBLEM TO BE SOLVED: To provide a copper interconnecting integrated circuit of low permittivity, where corrosion of interconnection is reduced, when a crack stopper adjacent to a trimmed edge is used also as a primary barrier to diffusion of oxygen in dielectrics. SOLUTION: A corresponding crack stopper element is formed simultaneously with formation of a circuit interconnection element. For example, a horizontal interconnection element has a structure corresponding to the crack stopper, and a via between interconnection layers also has a structure corresponding to the crack stopper.

公开(公告)号：AU2003217368A1

公开(公告)日：2003-09-09

申请号：AU2003217368

申请日：2003-02-06

Applicant: IBM

Inventor： FITZSIMMONS JOHN A ,  GATES STEPHEN M ,  MCGAHAY VINCENT J

IPC: H01L23/26 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit structure comprises a main dielectric layer having a top surface. A cavity having sidewalls is formed in the main dielectric layer. A liner is formed on the sidewalls of the cavity. A metal conductor such as copper is formed over the liner filling the lined cavity. A getter layer is formed in the structure which combines with oxygen/moisture to form inert reaction products thereof. The getter layer can be either a conductive material which can be included in the liner or a dielectric layer which can be formed on top of the main dielectric layer, buried in the main dielectric layer or below the main dielectric layer.

公开(公告)号：MY119966A

公开(公告)日：2005-08-30

申请号：MYPI20010319

申请日：2001-01-23

Applicant: IBM

Inventor： NYE HENRY A III ,  MCGAHAY VINCENT J ,  TALLMAN KURT A

IPC: H01L21/4763 ,  H01L21/3205 ,  H01L23/52 ,  H01L21/768 ,  H01L21/77 ,  H01L23/00 ,  H01L23/58

Abstract: A COPPER-INTERCONNECT (126, 136, 146), LOW-K DIELECTRIC (10) INTEGRATED CIRCUIT HAS REDUCED CORROSION OF THE INTERCONNECT WHEN THE CRACKSTOP (2) NEXT TO THE KERF IS ALSO USED AS THE PRIMACY BARRIER TO OXYGEN DIFFUSION THROUGH THE DIELECTRIC, WITH CORRESPONDING ELEMENTS (112, 122, 132, 142) OF THE CRACKSTOP BEING CONSTRUCTED SIMULTANEOUSLY WITH THE CIRCUIT INTERCONNECT ELEMENTS; E.G. HORIZONTAL INTERCONNECT ELEMENTS HAVE A CORRESPONDING STRUCTURE IN THE CRACKSTOP AND VIAS BETWEEN INTERCONNECT LAYERS HAVE CORRESPONDING STRUCTURES IN THE CRACKSTOP.