公开(公告)号：DE10206367A1

公开(公告)日：2003-09-04

申请号：DE10206367

申请日：2002-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EGERER JENS ,  FEURLE ROBERT ,  BORST THOMAS

IPC: G11C11/406

公开(公告)号：DE10203357A1

公开(公告)日：2003-08-14

申请号：DE10203357

申请日：2002-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WURZER HELMUT ,  FEURLE ROBERT ,  BAUCH LOTHAR ,  VOIGT INA

IPC: G03F1/00 ,  G03F1/36 ,  G03F1/14

Abstract: A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in the imaging properties of the main structures which are disposed at an edge of a region containing a multiplicity of main structures. In particular, constrictions at the structures can be significantly reduced or completely avoided and/or a so-called "tilting" of the structures under non-optimum focus conditions is significantly reduced or completely avoided.

公开(公告)号：DE10124278A1

公开(公告)日：2002-11-28

申请号：DE10124278

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT

IPC: G11C7/10 ,  G11C11/407

Abstract: A controller (2) retrieves data signal from specific memory cell and records data signal to specific memory cells based on received access commands. A configuration value containing Column Address Strobe (CAS) latency value and burst access value is received by the controller based on the commands.

公开(公告)号：DE10102350A1

公开(公告)日：2002-08-08

申请号：DE10102350

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT

IPC: G11C7/10 ,  G11C11/407

Abstract: An integrated memory has a plurality of memory cell arrays. The memory cell arrays are in each case assigned a decoder for selecting bit lines and word lines. In order to trigger an access cycle for a memory cell access, a write command or a read command with an active state is generated. Within the access cycle, under the control of a control circuit, respective decoders of the memory cell arrays are driven and data of each of the memory cell arrays are successively read out or written in for as long as the read command or write command remains in the active state. As a result, it is possible to set a comparatively large variable burst length of the memory. A method for operating an integrated memory is also provided.

公开(公告)号：DE19961518A1

公开(公告)日：2001-07-05

申请号：DE19961518

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT

IPC: G11C7/06 ,  G11C7/00

Abstract: A method for operating a current sense amplifier having a latch configuration improves the signal-to-noise ratio by setting the supply voltage for the latch configuration to be greater than a voltage which is present at the input of the current sense amplifier.

公开(公告)号：DE19944248A1

公开(公告)日：2001-03-29

申请号：DE19944248

申请日：1999-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT

IPC: H03K19/0175 ,  G11C11/4093 ,  H03K3/3565 ,  H03K19/00

Abstract: An integrated semiconductor circuit has two modes of operation and has several input buffers (IB1;IBn) which each have a terminal for an input signal (IN1;INn), and has at least one input buffer (IB1) for controlling switch-over between the operating modes through its input signal. The input buffer (IB1) for controlling the switch-over of the operating modes has a driver circuit (10) with an inverter circuit (11) which can be operated depending on requirements, in the first and second operating mode. The remaining input buffers (IB2;IBn) each has a difference amplifier circuit (DA) which is switched off in the second operating mode. The first operating mode is specifically used for normal operation and the second operating mode for current-saving operation of the semiconductor circuit (1).

公开(公告)号：DE10126310B4

公开(公告)日：2006-05-18

申请号：DE10126310

申请日：2001-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAEUBER ANDREAS ,  DORTU JEAN-MARC ,  SCHMOELZ PAUL ,  FEURLE ROBERT

IPC: H01L23/50 ,  H01L23/498 ,  H01L23/64 ,  H01L25/10

Abstract: A circuit board device (14) has a number of circuit board pads (19) for joining the circuit board device to the memory chip (12), in which the circuit board pads are arranged at least in one columnar arrangement, a number of data terminals for data-input and data-output, in which the data terminals are arranged in at least two columnar arrangements, which preferably extend mainly parallel to the arrangement of the circuit board pads (19). An Independent claim is given for (A) a semiconductor memory (storage) device, (B) use of a circuit board device.

公开(公告)号：DE59911518D1

公开(公告)日：2005-03-03

申请号：DE59911518

申请日：1999-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

IPC: H01L21/60 ,  G01R31/28 ,  G01R31/3185 ,  G11C11/401

Abstract: The semiconductor chip has bonding pads (IOP) to exchange input and output data, which can be preset for one of several possible data input/output organization forms (DQ4,DQ8). Not all of the bonding pads are used in normal use. All the bonding pads are connected to external connectors. The semiconductor chip has an altered input/output organization form, so that bonding pads not used in normal use are used in the test operation.

公开(公告)号：DE10206367C2

公开(公告)日：2003-12-11

申请号：DE10206367

申请日：2002-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EGERER JENS ,  FEURLE ROBERT ,  BORST THOMAS

IPC: G11C11/406

公开(公告)号：DE10150498C2

公开(公告)日：2003-08-07

申请号：DE10150498

申请日：2001-10-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PLAETTNER ECKEHARD ,  FEURLE ROBERT ,  PLAN MANFRED

IPC: G11C7/06

Abstract: A semiconductor memory apparatus includes a memory cell array having a multiplicity of data lines and a multiplicity of local amplifiers, each of the local amplifiers being associated with a data line. An amplifier group includes at least two amplifiers selected from the multiplicity of local amplifiers. Each amplifier has at least a pair of selection transistors for selecting a particular amplifier from the amplifier group. The selection transistors have a common gate, an unshared intrinsic diffusion region, and a shared intrinsic diffusion region, the shared intrinsic diffusion region being shared with an adjacent selection transistor from an adjacent amplifier.