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    PHASE SHIFTING MASK
    1.
    发明申请
    PHASE SHIFTING MASK 审中-公开
    相SLIDE MASK

    公开(公告)号：WO03054627A2

    公开(公告)日：2003-07-03

    申请号：PCT/DE0204321

    申请日：2002-11-25

    Applicant: INFINEON TECHNOLOGIES AG ,  HENNIG MARIO ,  KOEHLE RODERICK ,  KUNKEL GERHARD ,  PFORR RAINER ,  VOIGT INA

    Inventor： HENNIG MARIO ,  KOEHLE RODERICK ,  KUNKEL GERHARD ,  PFORR RAINER ,  VOIGT INA

    IPC: G03F1/00 ,  G03F1/14

    CPC classification number: G03F1/30

    Abstract: The invention relates to a phase shifting mask (8) having symmetrical structures (1, 2) for the production of adjacent pairs (5) of structures (1', 2') on a semiconductor wafer (9), such as pairs of trench capacitors for memory modules, the structures (1, 2) inside the pair having a phase deviation difference of 180 DEG in relation to each other. The dimensions of the structures at the limit of resolution of the lighting system enable the influence of lens aberrations on the difference in line width created between the right and the left to be reduced. The invention also relates to a method for producing the structures (1', 2') on the wafer (9), consisting of a step in which the phase attribution to the right structure (2) or left structure (1) is selected according to the sign of the difference in line width when said difference is measured without phase attribution, using the same lighting system.

    Abstract translation: 在一个相位罩（8）具有对称结构（1，2）用于制备接近半导体晶片（9），在结构上的相互对置的对（5）（1”，2' ），诸如对于具有结构的存储器器件严重电容器对（1，2） 该对对180°的彼此Phasenhubunterschied内。 当躺在由透镜像差的影响的曝光系统结构的尺寸的分辨率极限降低到所得到的左右线宽差。 一种用于结构的晶片（9）的制备（1”，2' ）的过程包括选择（2）或左结构（1），这取决于线的符号宽度差的权利，相位指定的demn步骤的使用时 没有相位分配相同的成像系统被测量。

    Forming alignment mask for semiconductor memory unit, includes stages of electrode formation, dielectric deposition, selective filling, collar- and hollow formation
    3.
    发明专利
    Forming alignment mask for semiconductor memory unit, includes stages of electrode formation, dielectric deposition, selective filling, collar- and hollow formation 未知

    公开(公告)号：DE102004002205B3

    公开(公告)日：2005-06-23

    申请号：DE102004002205

    申请日：2004-01-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEITZ MIHEL ,  SACHSE HERMANN ,  MOLL HANS-PETER ,  FROEHLICH HANS-GEORG ,  VOIGT INA

    IPC: H01L21/8242 ,  H01L23/544

    Abstract: A semiconductor wafer with substrate (5) is prepared. A deep trench (12) and at least one depression are formed in the substrate. An external capacitor electrode is formed in the lower region of the trench (12). Dielectric is deposited in the lower region of the trench. An inner capacitor electrode is formed by filling the lower region only, with conductive material. A collar (42) is formed in the upper region of the side walls of the trench and the depression. Trench and depression are filled in the upper region with filling material (48), so that in the region of the depression a hollow representing the alignment mask remains. A semiconductor wafer with substrate (5) is prepared. A deep trench (12) and at least one depression are formed in the substrate. An external capacitor electrode is formed in the lower region of the trench (12). Dielectric is deposited in the lower region of the trench. An inner capacitor electrode is formed by filling the lower region only, with conductive material. A collar (42) is formed in the upper region of the side walls of the trench and the depression. Trench and depression are filled in the upper region with filling material (48), so that in the region of the depression a hollow representing the alignment mask remains. A liner layer (16) is deposited completely over the whole area of the substrate (5). Full-area deposition of a non-doped amorphous silicon layer follows, over the liner layer. A resist layer is deposited over the non-doped amorphous silicon layer. The resist layer is structured so that the upper side of the semiconductor wafer is covered by it, in the region of the hollow. Angled implantation of a dopant follows, forming a doped amorphous silicon layer. The resist layer is removed. Selective etching of the non-doped amorphous silicon layer, bares the underlying liner layer. This is then removed and the filling material in the trench and in the depression is etched. An independent claim is included for the corresponding semiconductor arrangement with alignment mask and trench capacitor.

    8.
    发明专利
    未知

    公开(公告)号：DE10203357A1

    公开(公告)日：2003-08-14

    申请号：DE10203357

    申请日：2002-01-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WURZER HELMUT ,  FEURLE ROBERT ,  BAUCH LOTHAR ,  VOIGT INA

    IPC: G03F1/00 ,  G03F1/36 ,  G03F1/14

    Abstract: A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in the imaging properties of the main structures which are disposed at an edge of a region containing a multiplicity of main structures. In particular, constrictions at the structures can be significantly reduced or completely avoided and/or a so-called "tilting" of the structures under non-optimum focus conditions is significantly reduced or completely avoided.

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