公开(公告)号：WO0041459A3

公开(公告)日：2001-05-10

申请号：PCT/DE0000047

申请日：2000-01-05

Applicant: INFINEON TECHNOLOGIES AG ,  SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  TEWS HELMUT

Inventor： SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  TEWS HELMUT

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

Abstract: The invention relates to a semiconductor element with at least one layer of tungsten oxide (WOx), optionally in a structured tungsten oxide (WOx) layer. The inventive semiconductor element is characterized in that the relative permittivity ( epsilon r) of the tungsten oxide layer (WOx) is higher than 50.

Abstract translation: 根据本发明，具有至少一个氧化钨的层（的WOx），半导体装置任选地提供氧化钨（WO x）的图形层。 本发明的半导体装置的特征在于，所述氧化钨（WO x）的相对介电常数（ε-r）为低于50更大

公开(公告)号：WO0034991A3

公开(公告)日：2000-11-16

申请号：PCT/DE9903878

申请日：1999-12-03

Applicant: INFINEON TECHNOLOGIES AG ,  POMPL THOMAS ,  WURZER HELMUT ,  REBITZER WOLFGANG ,  GAERTNER THOMAS ,  KRAHL KERSTIN ,  WEGE STEPHAN ,  GEHRING OLIVER

Inventor： POMPL THOMAS ,  WURZER HELMUT ,  REBITZER WOLFGANG ,  GAERTNER THOMAS ,  KRAHL KERSTIN ,  WEGE STEPHAN ,  GEHRING OLIVER

IPC: C23C8/02 ,  C23C14/58 ,  C23C28/00 ,  H01L21/28 ,  H01L21/311

CPC classification number: C23C14/5853 ,  C23C8/02 ,  C23C28/00 ,  H01L21/28167 ,  H01L21/31116 ,  H01L29/511

Abstract: The invention relates to a method of producing a metal oxide film. The inventive method comprises the following steps: a) providing a barrier film, b) applying a metal film onto the barrier film, and c) thermally oxidizing the metal film in an oxygen atmosphere, thereby producing a metal oxide film (3').

Abstract translation: 根据本发明，提供了一种用于生产金属氧化物层的方法。 在这种情况下，本发明的方法包括以下步骤：a）阻挡层设置，b）中在阻挡层上，金属层被沉积​​，以及c）将金属层在氧气氛中进行热氧化，从而产生一个金属氧化物层（3“）。

公开(公告)号：DE19947053C1

公开(公告)日：2001-05-23

申请号：DE19947053

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  KARCHER WOLFRAM

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitor comprises: trench (108) having an upper region (109) and a lower region (111) formed in substrate (101); insulating collar (168) formed in upper region of trench; trenched sink (170) formed in the substrate and partially penetrating lower region of trench; a dielectric layer (164) made of tungsten oxide as capacitor dielectric; and a conducting trench filling (161) in the trench. An Independent claim is also included for a process for the production of the trench capacitor. Preferred Features: The conducting trench filling is made of a tungsten-containing material. A barrier layer made of silicon oxide, oxynitride, tungsten nitride, titanium nitride or tantalum nitride is arranged between the dielectric layer and the substrate.

公开(公告)号：DE10029658C2

公开(公告)日：2003-01-09

申请号：DE10029658

申请日：2000-06-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHREMS MARTIN ,  WURZER HELMUT ,  KRASEMANN ANKE ,  POMPL THOMAS

IPC: H01L21/316 ,  H01L27/08 ,  H01L21/314 ,  H01L21/336 ,  H01L21/822

Abstract: Method for fabricating a barrier layer having the following steps, namely oxidation of a substrate (1) composed of silicon in order to produce a substrate oxide (2) on the surface of the substrate (1); production of an oxygen-impervious layer (4) at the interface between the substrate oxide layer (2) and the substrate (1), the oxygen-impervious layer (4), as barrier, preventing the formation of metal silicide compounds between applied metal and the substrate silicon; etching of the substrate oxide layer (2) until the underlying oxygen-impervious layer (4) is uncovered.

公开(公告)号：DE10121011A1

公开(公告)日：2002-11-14

申请号：DE10121011

申请日：2001-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  WURZER HELMUT

IPC: H01L21/768 ,  H01L21/8242

Abstract: Process for doping bit line contact holes comprises simultaneously opening contact holes (5) in the cell field and also further contact holes in peripheral circuits of the chip; and carrying out unmasked n-type doping of all the contact holes. An Independent claim is also included for a semiconductor arrangement with contact holes. Preferred Features: In a previous step, an n-type implantation does in the drain/source doping of the contact holes in the peripheral circuits corresponding to the unmasked n-type doping is reduced. The bit line contact (CB) is filled with tungsten.

公开(公告)号：DE10011885C2

公开(公告)日：2002-10-24

申请号：DE10011885

申请日：2000-03-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WURZER HELMUT ,  LANGHEINRICH WOLFRAM

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/8242

公开(公告)号：DE59707373D1

公开(公告)日：2002-07-04

申请号：DE59707373

申请日：1997-07-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PENKA VOLKER ,  MAHNKOPF REINHARD ,  WURZER HELMUT

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/285 ,  H01L21/768

Abstract: A method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped or siliconized zones in a semiconductor body. Fluorine ions are implanted into the heavily doped or siliconized zone in the vicinity of a contact hole before a titanium layer is applied to the heavily doped or siliconized zone in the vicinity of the contact hole. As a result of the fluorine, any oxide layers present in the contact hole region can be broken up by less titanium, with the result that a thinner titanium layer is sufficient. In addition, the formation of titanium silicide in the contact hole is promoted.

公开(公告)号：DE10021095A1

公开(公告)日：2001-10-31

申请号：DE10021095

申请日：2000-04-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERBER MARTIN ,  WURZER HELMUT ,  POMPL THOMAS

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/314

Abstract: The method involves implanting ions (5) in a surface layer (4) of the semiconductor substrate (2) to form a first dielectric layer (7). A thermal oxidation process is performed to form a second dielectric layer (8) on the first dielectric layer (7). The semiconductor substrate is preferably a silicon substrate. The implanted ions are nitrogen ions (5). Prior to forming the dielectric, a cleaning process may be performed to clean the semiconductor substrate surface.

公开(公告)号：DE10203358A1

公开(公告)日：2003-04-03

申请号：DE10203358

申请日：2002-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUNKEL GERHARD ,  SACHSE HERMANN ,  BAUCH LOTHAR ,  WURZER HELMUT

IPC: G03F1/32 ,  G03F1/00 ,  G03F1/38 ,  G03F1/14

公开(公告)号：DE10135870C1

公开(公告)日：2003-02-20

申请号：DE10135870

申请日：2001-07-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WURZER HELMUT

IPC: H01L21/8234

Abstract: Production of an integrated semiconductor circuit comprises depositing a first layer sequence (10) having a lowermost layer (11) made from oxidizable material arranged on a substrate covered with a gate oxide layer (3); anisotropically etching the layer sequence; oxidizing the lowermost layer of the first layer sequence; depositing a second layer sequence on the substrate so that gate structures are covered in a first surface region; and isotropically etching the second layer sequence. Preferred Features: A first etch stop layer (13) is deposited as the uppermost layer of the first layer sequence to cover the upper sides of the gate structures. An additional layer is deposited as an etch stop layer on a first surface region. The etch stop layers are made from silicon nitride or tungsten oxide or aluminum oxide.