公开(公告)号：DE59803115D1

公开(公告)日：2002-03-28

申请号：DE59803115

申请日：1998-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SICHERT CHRISTIAN

IPC: H03K17/04 ,  H03K17/60 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185

Abstract: The input amplifier includes MOS-transistors (6,7) and a single-ended current disconnection for input signals having steep edges. Also provided is at least one transistor (7) having an electrode connected to the output. A further transistor, e.g. NMOS, (21) prevents complete switch-off of the transistor (7), e.g. PMOS so that the electrode (QN) can be pulled up on to the operating voltage as soon as the input signal with the steep edge is present. This NMOS-transistor (21) has a higher threshold voltage than that of the first PMOS-transistor (7).

公开(公告)号：DE102005042269A1

公开(公告)日：2006-04-13

申请号：DE102005042269

申请日：2005-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

IPC: G11C7/22

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

公开(公告)号：DE102005042269B4

公开(公告)日：2008-09-18

申请号：DE102005042269

申请日：2005-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

IPC: G11C7/22

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

公开(公告)号：DE102005055185A1

公开(公告)日：2006-06-08

申请号：DE102005055185

申请日：2005-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  BACHA ABDALLAH ,  SICHERT CHRISTIAN ,  SAVIGNAC DOMINIQUE ,  GREGORIUS PETER ,  WALLNER PAUL

IPC: G11C7/22

Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

公开(公告)号：DE59801145D1

公开(公告)日：2001-09-13

申请号：DE59801145

申请日：1998-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SICHERT CHRISTIAN ,  MANYOKI ZOLTAN

IPC: H03K17/04 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0185

Abstract: An input amplifier for input signals with steep leading and trailing edges and including at least one transistor (7) having an electrode connected to an output (20). A delay element e.g. a transistor (21) is provided for preventing complete, premature switch off of the input amplifier so that the current through the input amplifier is only switched off after the input signal has been evaluated. The delay element (X) has a load-side-connected current source (21) via which the output (20) is fed back for current supply of the amplifier.