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    1.
    发明专利
    未知

    公开(公告)号：DE102005051943A1

    公开(公告)日：2006-07-06

    申请号：DE102005051943

    申请日：2005-10-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

    IPC: G11C7/10

    Abstract: The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2 n bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2 n data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2 n of the sets of addressable memory cells.

    3.
    发明专利
    未知

    公开(公告)号：DE102005056351A1

    公开(公告)日：2006-07-13

    申请号：DE102005056351

    申请日：2005-11-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN

    IPC: G11C11/409 ,  G11C7/22

    Abstract: One embodiment of the present invention provides a memory device comprising a plurality of sets of memory banks, wherein each memory bank includes a memory array and is adapted to be read out in a data access; a plurality of internal data buses and a plurality of internal command and address buses connected to the plurality of sets of memory banks, respectively, such that each set of memory banks is associated with one of the internal data buses and one of the internal command and address buses; a command and address port for receiving command and address data from outside; and a command and address unit to direct the received command and address data to one of the sets of memory banks via the associated command and address bus, depending on the address data; and a data output unit for receiving data read out from one set of memory banks via the respective internal data bus in the data access and for serially outputting the received data.

    4.
    发明专利
    未知

    公开(公告)号：DE102004052612A1

    公开(公告)日：2006-05-04

    申请号：DE102004052612

    申请日：2004-10-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  GREGORIUS PETER ,  SICHERT CHRISTIAN ,  WALLNER PAUL

    IPC: G11C7/10 ,  G06F11/14 ,  G11C11/4093

    Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission of the write datum detected as erroneous. This repeat request signal can be transmitted either as a single-bit signal or as a multibit signal (e.g., serially as an individual signal line to a superordinate memory controller).

    5.
    发明专利
    未知

    公开(公告)号：DE102005042427A1

    公开(公告)日：2006-04-13

    申请号：DE102005042427

    申请日：2005-09-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

    IPC: G06F12/00

    Abstract: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

    6.
    发明专利
    未知

    公开(公告)号：DE59915043D1

    公开(公告)日：2009-08-06

    申请号：DE59915043

    申请日：1999-07-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SICHERT CHRISTIAN ,  BARTENSCHLAGER RAINER

    IPC: G05F1/575 ,  G05F1/46

    Abstract: An integrated circuit includes a voltage regulator for generating an internal supply voltage. The voltage regulator has one input for applying an actual value and one input for applying a reference voltage as a desired value. The actual value is generated through the use of a first voltage divider from the internal supply voltage. A sensitivity of the voltage regulator is dependent on a resistance of at least one resistor element of the first voltage divider. A second voltage divider, which is connected parallel to the first voltage divider, has the same voltage divider ratio as the first voltage divider and is activatable and deactivatable by at least one switch element.

    9.
    发明专利
    未知

    公开(公告)号：DE59811858D1

    公开(公告)日：2004-09-30

    申请号：DE59811858

    申请日：1998-06-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SICHERT CHRISTIAN ,  KAISER ROBERT ,  WIRTH NORBERT

    IPC: H03K5/02 ,  H03K5/08 ,  H03K17/14 ,  H03K17/687 ,  H03K19/0185

    Abstract: The circuit arrangement includes a device (10) for generating digital signals, with a voltage connection (8) for the supply of an external reference voltage to the device, and a voltage generator (2) for the production of an internal reference voltage which is supplied to the device over a switch (4). A level converter (6) is provided for the control of the switch, whereby a switch signal for the switching of the switch is raised on a level lying above the switching threshold of the switch. An output coupling capacitor (C1) is connected between the output of the voltage generator and a first supply voltage (VSS).

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