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公开(公告)号:DE102004005645B4
公开(公告)日:2006-01-12
申请号:DE102004005645
申请日:2004-02-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: TROVARELLI OCTAVIO , BRINTZINGER AXEL , LEIBERG WOLFGANG
IPC: H01L21/44 , H01L21/4763 , H01L21/768
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公开(公告)号:DE10356119B3
公开(公告)日:2005-08-18
申请号:DE10356119
申请日:2003-11-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BRINTZINGER AXEL , RUCKMICH STEFAN , TROVARELLI OCTAVIO
IPC: H01L21/4763 , H01L21/60 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/40
Abstract: An electronic component includes compliant elevations having electrical contact areas for contact-connecting the component to an electronic circuit. The compliant elevations are arranged on a surface of the component and the electrical contact areas are arranged on the tip of the compliant elevations. The electrical contact with the electronic circuit is embodied by means of electrical conductive tracks arranged on the surface of the component. The conductive tracks ascend on the outer surfaces of the compliant elevations to the electrical contact areas.
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公开(公告)号:DE10254547A1
公开(公告)日:2004-06-17
申请号:DE10254547
申请日:2002-11-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor: TROVARELLI OCTAVIO
IPC: H01L25/065 , H05K1/18 , H05K3/28 , H01L25/04
Abstract: The module assembly consists of a printed circuit board (2) with a number of chips mounted on one or both sides in a defined pattern and enclosed by a housing (10,11). The protection arrangement has a distance holder (8) that fills the gaps on the circuit board between chips, at least partly passes over the edges of the chips and has a lightly greater height than the chips. The inner surfaces of the housing rest on the distance holder.
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公开(公告)号:DE102004023752B4
公开(公告)日:2006-08-24
申请号:DE102004023752
申请日:2004-05-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BRINTZINGER AXEL , RUCKMICH STEFAN , TROVARELLI OCTAVIO
IPC: H01L21/60 , H01L21/3213 , H01L21/768
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公开(公告)号:DE102004050476B3
公开(公告)日:2006-04-06
申请号:DE102004050476
申请日:2004-10-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor: TROVARELLI OCTAVIO , BRINTZINGER AXEL , UHLENDORF INGO , RUCKMICH STEFAN , WALLIS DAVID
Abstract: Masking layers (3) are applied and structured on both sides of the substrate wafer (1), to form a first contact location (6) on the first surface (11) and a second contact location (6) on the second surface (12). A protective layer is applied to the second surface, to protect the masking and contact on that side, during the following stages. A conductor structure (7) is deposited on the first surface (11), covering the first contact location. The protective layer on the second surface is removed, and the second conductor structure (7) is applied, to cover the second contact location on the second surface (12). In a further stage, a protective layer is applied to the first surface. Application of the masking layer on the first and second surfaces comprises evaporation, immersion coating and gas phase deposition. Structuring of the masking layer is carried out by lithographic- and etching processes. The first and/or second protective layer is applied using immersion coating, spray coating or rotation coating. The first and/or second protective layers are formed from plastic film, which is adhered or laminated to the respective surface. The substrate wafer is prepared from a silicon substrate.
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公开(公告)号:DE102004023897A1
公开(公告)日:2005-12-15
申请号:DE102004023897
申请日:2004-05-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BRINTZINGER AXEL , TROVARELLI OCTAVIO , WALLIS DAVID , RUCKMICH STEFAN
IPC: H01L21/288 , H01L21/768 , H01L23/31 , H01L23/528 , H01L23/532
Abstract: The method involves galvanically depositing the copper cores of the tracks and contact pads in the mask openings of a resist mask made of positive resist, then removing their edges by a further lithographic process. The copper cores are then completely enclosed with a nickel-gold layer before the positive resist mask is removed. To expose the edges, the positive resist mask is completely removed and a second negative-resist mask is created so that the copper core of the track and contact pad including a completely surrounding edge region is kept free.
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公开(公告)号:DE102004023752A1
公开(公告)日:2005-12-15
申请号:DE102004023752
申请日:2004-05-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BRINTZINGER AXEL , RUCKMICH STEFAN , TROVARELLI OCTAVIO
IPC: H01L21/3213 , H01L21/60 , H01L21/768
Abstract: The method involves applying a sacrificial layer (6) to the redistribution layer (4) for protecting the copper layer (3) below during subsequent etching processes. The resist mask is removed in a lift-off step, and the seed layer is then removed by etching.
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公开(公告)号:DE102004031465A1
公开(公告)日:2005-09-08
申请号:DE102004031465
申请日:2004-06-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BRINTZINGER AXEL , TROVARELLI OCTAVIO
IPC: H01L21/60 , H01L23/50 , H01L23/525
Abstract: An integrated circuit (1) has a bare fuse element (3) with a wiring area that can be cut through. A protective layer is applied over the wiring area of the fuse element. The surface of the integrated circuit is processed so as to form a re-wiring lead (7). The protective layer is removed so as to bare the wiring area of the fuse element. An independent claim is also included for an integrated circuit designed as a water level package with a re-wiring lead on a surface.
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公开(公告)号:DE10318074A1
公开(公告)日:2004-12-09
申请号:DE10318074
申请日:2003-04-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor: TROVARELLI OCTAVIO , BRINTZINGER AXEL
IPC: H01L21/56 , H01L21/78 , H01L23/31 , H01L23/485 , H01L21/60
Abstract: Process for improving the mechanical properties of BOC module arrangements comprises providing a wafer (1) or chips after their separation and before their assembly on a circuit board with a casting compound (5) so that the tips of the three-dimensional structures (2) protrude from them.
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公开(公告)号:DE10318078A1
公开(公告)日:2004-11-25
申请号:DE10318078
申请日:2003-04-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BRINTZINGER AXEL , TROVARELLI OCTAVIO
Abstract: Protecting the wiring on wafers/chips comprises covering the wafer (1) with the wiring on its whole surface with an organic layer (12) to protect the wiring from corrosion and oxidation and form a sealed coating of the metal surface of the wiring.
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