公开(公告)号：DE102004005022A1

公开(公告)日：2005-08-25

申请号：DE102004005022

申请日：2004-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TROVARELLI OCTAVIO ,  LEIBERG WOLFGANG

IPC: H01L21/768 ,  H01L23/532 ,  H05K3/10 ,  H05K3/24 ,  H01L51/10 ,  H05K1/09

Abstract: A method for fabricating a metallic conductor path with copper-nickel-gold layer structure, in which the copper core of the conductor path is electrically deposited on a copper seed layer (4) with a diffusion barrier arranged under it. Initially a dielectric mask (9) is formed so that the mask structure comprises the conductor path being fabricated, followed by extensive application of a copper-seed layer (4) carrying on the structure of the dielectric mask (9). A resist-mask is formed on the copper seed layer (4) by a first lithographic structuring of the positive resist, followed by galvanic deposition of the copper core (3) on the exposed copper seed layer (4). A second lithographic structuring of the resist mask follows, with subsequent application of nickel-gold-layer on the copper core (3) and removal of the resist mask and etching of the diffusion barrier (10) and the copper seed layer (4).

公开(公告)号：DE10032282A1

公开(公告)日：2002-01-24

申请号：DE10032282

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUCH LOTHAR ,  LEHR MATTHIAS ,  LEIBERG WOLFGANG ,  SPINLER STEFAN

IPC: G03F7/09 ,  H01L21/311 ,  H01L21/768 ,  G03F7/20

Abstract: Lithographic exposure and structuring comprises preparing a substrate (1); applying an anti-refection layer (4) made up of several layers on the substrate; applying a material layer (2) to be treated on the anti-reflection layer; applying a photoresist layer (3) directly to the material layer; and exposing and structuring the photoresist layer so that the material layer is exposed in pre-determined sections for local selective treatment. An Independent claim is also included for the production of a metallic conducting pathway comprising forming a structured photoresist layer as above; removing the material layer in the exposed sections; optionally carrying out the previous two steps; depositing metallic conducting pathway material in the etched recess; and optionally back-polishing the metallic material. Preferred Features: The anti-refection layer is a SiON layer and the material layer is a SiO2 or nitride layer.

公开(公告)号：DE102004005645B4

公开(公告)日：2006-01-12

申请号：DE102004005645

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  LEIBERG WOLFGANG

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768

公开(公告)号：DE10030445A1

公开(公告)日：2002-01-10

申请号：DE10030445

申请日：2000-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS RENE ,  LEIBERG WOLFGANG ,  RUF ALEXANDER ,  LEHR MATTHIAS ,  DRESCHER DIRK

IPC: H01L23/525

Abstract: The connection element in an integrated circuit has a layer structure arranged between two conductive structures. The layer structure has a dielectric layer which can be destroyed by application of a predetermined voltage. At least one conductive structure is composed of tungsten. The conductive structure adjoins a conductive layer made of tungsten or a tungsten compound, which is a constituent part of the layer structure and which adjoins the dielectric layer.

公开(公告)号：DE10021098C1

公开(公告)日：2001-09-20

申请号：DE10021098

申请日：2000-04-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS ,  LEIBERG WOLFGANG

IPC: H01L21/768 ,  H01L23/525

Abstract: Production of conducting pathways on an integrated chip comprises: (i) applying a stacked dielectric layer; (ii) carrying out photolithography to define contact holes (30); (iii) etching the holes; (iv) applying conducting material and removing outside of the holes; (v) applying an insulating layer (50); (vi) carrying out photolithography to define conducting pathways; (vii) etching conducting pathway trenches (80); and (viii) applying conducting material and removing outside of the trenches. Production of conducting pathways on an integrated chip comprises: (a) applying a stacked dielectric layer consisting of a lower (21) and an upper dielectric layer (22) with an antireflection layer (60) arranged between them; (b) carrying out photolithography to define contact holes (30) in the dielectric layer; (c) etching the holes in the stacked layer; (d) applying conducting material and removing the material outside of the holes so that recesses (40) are formed over the contact holes; (e) applying an insulating layer (50); (f) carrying out photolithography to define conducting pathways in the region of individual contact holes on the insulating layer; (g) etching conducting pathway trenches (80) in the insulating layer and the upper dielectric layer lying underneath so that the antireflection layer acts as an etch stop; and (h) applying conducting material and removing the material outside of the trenches and the recesses over the contact holes. Preferred Features: The insulating layer is made from silicon nitride. The antireflection layer is a light-absorbing inorganic material, especially silicon oxynitride. Polycrystalline silicon is used to fill the contact holes and tungsten is used to fill the trenches and the recesses above the contact holes.

公开(公告)号：DE50111519D1

公开(公告)日：2007-01-11

申请号：DE50111519

申请日：2001-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS DR ,  LEIBERG WOLFGANG

IPC: H01L21/768 ,  H01L23/525

Abstract: A method for fabricating a wiring plane with antifuses is described. During the fabrication of the wiring plane on a semiconductor chip with the antifuses, provision is made of a buried antireflection layer in a dielectric layer. In the dielectric layer contact holes are formed, as a result of which only one etching step has to be carried out for the photolithography for forming interconnect trenches above the contact holes.

公开(公告)号：DE102004005645A1

公开(公告)日：2005-09-22

申请号：DE102004005645

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  LEIBERG WOLFGANG

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768

公开(公告)号：DE10054969A1

公开(公告)日：2002-03-28

申请号：DE10054969

申请日：2000-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  LEHR MATTHIAS UWE

IPC: C23F4/00 ,  H01L21/311 ,  H01L21/314 ,  H01L21/3213

Abstract: Structuring metal layers by lithography, especially i-line lithography or DIN lithography and subsequent plasma etching, especially reactive ion etching, comprises applying the required antireflection layer (3) as a dielectric layer before the reactive ion etching of the uppermost metal layer of several metal layers placed on top of each other. Preferred Features: The thickness of the dielectric antireflection layer is chosen so that the light used in the lithographic process undergoes minimal reflection. The dielectric antireflection layer forms a highly selective etching mask in combination with a thin photoresist layer (4). The antireflection layer comprises silicon oxy nitride.

公开(公告)号：DE19945425A1

公开(公告)日：2001-04-19

申请号：DE19945425

申请日：1999-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  LEHR MATTHIAS UWE ,  LUEKEN ELKE ,  MOLL PETER ,  VOGT MIRKO ,  KIESLICH ALBRECHT

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/321 ,  G03F7/20

Abstract: Structuring a metal layer (M) during semiconductor finishing comprises applying a lacquer layer (L) to a semiconductor substrate; structuring the lacquer layer using lithography and producing an etching mask; and structuring the metal layer using the mask. Initially a hard mask is applied to the metal layer and the lacquer layer is applied to the mask, where the lacquer layer is thin so that only the mask and not the metal layer can be structured with the aid of the lacquer layer. The hard mask is structured to form an etching mask with the aid of the structured lacquer layer. The metal layer is structured with the hard mask as an etching mask. Preferred Features: The hard mask has a first layer (H1) of an oxide, preferably silicon dioxide, and a second layer (H2) to reduce reflection and made of silicon nitride. The metal layer is made of aluminum and/or copper.

公开(公告)号：DE102004005022B4

公开(公告)日：2006-02-16

申请号：DE102004005022

申请日：2004-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TROVARELLI OCTAVIO ,  LEIBERG WOLFGANG

IPC: H01L21/768 ,  H01L23/532 ,  H01L51/10 ,  H05K1/09 ,  H05K3/10 ,  H05K3/24

Abstract: A method for fabricating a metallic conductor path with copper-nickel-gold layer structure, in which the copper core of the conductor path is electrically deposited on a copper seed layer (4) with a diffusion barrier arranged under it. Initially a dielectric mask (9) is formed so that the mask structure comprises the conductor path being fabricated, followed by extensive application of a copper-seed layer (4) carrying on the structure of the dielectric mask (9). A resist-mask is formed on the copper seed layer (4) by a first lithographic structuring of the positive resist, followed by galvanic deposition of the copper core (3) on the exposed copper seed layer (4). A second lithographic structuring of the resist mask follows, with subsequent application of nickel-gold-layer on the copper core (3) and removal of the resist mask and etching of the diffusion barrier (10) and the copper seed layer (4).