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    1.
    发明专利
    未知

    公开(公告)号：DE102004035080A1

    公开(公告)日：2005-12-29

    申请号：DE102004035080

    申请日：2004-07-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  UHLENDORF INGO ,  RUCKMICH STEFAN ,  WALLIS DAVID

    IPC: H01L23/12 ,  H01L23/522 ,  H01L23/528

    Abstract: An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor ( 10 ) being respectively arranged between adjacent conductors of the redistribution routing ( 1 ) and/or at least a second passivation ( 7 ) with a lower dielectric constant of a preferred "cold dielectric" being arranged between the redistribution routing ( 1 ) and the first passivation ( 2 ) on the active region of the chip ( 3 ).

    3.
    发明专利
    未知

    公开(公告)号：DE10356119B3

    公开(公告)日：2005-08-18

    申请号：DE10356119

    申请日：2003-11-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRINTZINGER AXEL ,  RUCKMICH STEFAN ,  TROVARELLI OCTAVIO

    IPC: H01L21/4763 ,  H01L21/60 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L29/40

    Abstract: An electronic component includes compliant elevations having electrical contact areas for contact-connecting the component to an electronic circuit. The compliant elevations are arranged on a surface of the component and the electrical contact areas are arranged on the tip of the compliant elevations. The electrical contact with the electronic circuit is embodied by means of electrical conductive tracks arranged on the surface of the component. The conductive tracks ascend on the outer surfaces of the compliant elevations to the electrical contact areas.

    Making wiring circuit panel, employs structured masking layers to define through-contact locations, with selective use of protective layers when depositing conductor structures
    5.
    发明专利
    Making wiring circuit panel, employs structured masking layers to define through-contact locations, with selective use of protective layers when depositing conductor structures 未知

    公开(公告)号：DE102004050476B3

    公开(公告)日：2006-04-06

    申请号：DE102004050476

    申请日：2004-10-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  UHLENDORF INGO ,  RUCKMICH STEFAN ,  WALLIS DAVID

    IPC: H01L23/50 ,  H01L21/48 ,  H05K7/20

    Abstract: Masking layers (3) are applied and structured on both sides of the substrate wafer (1), to form a first contact location (6) on the first surface (11) and a second contact location (6) on the second surface (12). A protective layer is applied to the second surface, to protect the masking and contact on that side, during the following stages. A conductor structure (7) is deposited on the first surface (11), covering the first contact location. The protective layer on the second surface is removed, and the second conductor structure (7) is applied, to cover the second contact location on the second surface (12). In a further stage, a protective layer is applied to the first surface. Application of the masking layer on the first and second surfaces comprises evaporation, immersion coating and gas phase deposition. Structuring of the masking layer is carried out by lithographic- and etching processes. The first and/or second protective layer is applied using immersion coating, spray coating or rotation coating. The first and/or second protective layers are formed from plastic film, which is adhered or laminated to the respective surface. The substrate wafer is prepared from a silicon substrate.

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