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    SEMICONDUCTOR INTEGRATED CIRCUIT
    13.
    发明专利
    SEMICONDUCTOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2000031425A

    公开(公告)日：2000-01-28

    申请号：JP17893899

    申请日：1999-06-24

    Applicant: SIEMENS AG ,  IBM

    Inventor： SCHREMS MARTIN ,  MANDELMAN JACK ,  HOEPFNER JOACHIM ,  SCHAEFER HERBERT ,  STENGL REINHARD

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: PROBLEM TO BE SOLVED: To reduce the rough surface on a side wall of a trench of a trench capacitor by forming the trench capacitor in the shape of a bottle with the lower part of the treanch being larger than the upper part and covering a collar and an epitaxial buried plate from inside with a node dielectric. SOLUTION: A trench capacitor 310 included in a DRAM cell 300 is formed in a silicon wafer substrate 301. A lower part of a trench has a larger diameter or width WL than the diameter or width WU of an upper part. The trench of such a shape is called a bottle trench. And, an epitaxial silicon (epi) layer 365 covers the lower part of the trench below a collar 368 from inside. The epi is doped with an n-type dopant such as As or P and is used as a buried plate of a capacitor. By covering the lower part of the trench by the epi layer from inside, the rough surface to be formed with a node dielectric can be reduced.

    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
    15.
    发明申请
    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
    双端口增益单元与侧面和顶部读取晶体管

    公开(公告)号：WO2007023011B1

    公开(公告)日：2007-07-12

    申请号：PCT/EP2006063581

    申请日：2006-06-27

    Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

    Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

    Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

    Abstract translation: 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

    ELECTRICALLY PROGRAMMABLE FUSE
    16.
    发明申请
    ELECTRICALLY PROGRAMMABLE FUSE 审中-公开
    电子可编程保险丝

    公开(公告)号：WO2007051765A3

    公开(公告)日：2007-06-28

    申请号：PCT/EP2006067883

    申请日：2006-10-27

    Applicant: IBM ,  IBM UK ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

    Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

    IPC: H01L23/525

    CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrically programmable fuse (eFuse) includes (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. The diode comprises an N+,p-,P+ or P+,n-,N+ structure.

    Abstract translation: 电可编程熔丝（eFuse）包括（1）衬底的绝缘氧化物层上的半导体层; （2）形成在半导体层中的二极管; 和（3）在二极管上形成的硅化物层。 二极管包括N +，p-，P +或P +，n-，N +结构。

    METHOD OF FORMING EMBEDDED SELF-ALIGNED STRAP IN DEEP STORAGE TRENCH, AND SEMICONDUCTOR DEVICE
    17.
    发明专利
    METHOD OF FORMING EMBEDDED SELF-ALIGNED STRAP IN DEEP STORAGE TRENCH, AND SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JP2000216354A

    公开(公告)日：2000-08-04

    申请号：JP2000005490

    申请日：2000-01-14

    Applicant: IBM ,  SIEMENS AG

    Inventor： MANDELMAN JACK ,  RADENS CARL ,  GRUENING ULRIKE

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an embedded self-aligned strap in a deep storage trench. SOLUTION: A spacer 42/52 is formed on the wall face of a recess on an already filled deep trench capacitor 30. A plug 46/54 is formed within the region between spacers. A photoresist is stuck onto the spacer 42/54 and the plug 46/54 and a peripheral material 40, and a part of the plug 46/54, the spacer 42/52, and the material 40 is exposed. The spacer part not covered with the photoresist is selectively etched. A board and a trench part exposed by the removal of the spacer are selectively etched. An isolation region 58 is formed within the space made etching.

    DRAM cell having annular signal transfer region
    18.
    发明专利
    DRAM cell having annular signal transfer region 未知

    公开(公告)号：CZ295847B6

    公开(公告)日：2005-11-16

    申请号：CZ20011964

    申请日：1999-11-26

    Applicant: IBM

    Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: In the present invention, there is disclosed a memory device (200) in a substrate having a trench with side walls in the substrate, said memory device (200) including bit line conductors (246) and word line conductors (230). Signal storage node has a first electrode (202), a second electrode (204) formed within the trench (252; DT), and a node dielectric (206) formed between the electrodes (202, 204). The signal transfer device has: an annular signal transfer region (222) with outer surface adjacent side walls (212) of the trench (252; DT), an inner surface, a first and a second end; a first diffusion region (218) coupling the first end of the signal transfer region (222) to the second electrode (204) of the signal storage node; a second diffusion region (220) coupling the second end of signal transfer region (222) to the bit line conductor (246); a gate insulator (224) coating the inner surface of signal transfer region (222); and a gate conductor (226) coating the gate insulator (224) and coupled to the word line conductor (230). A conductive connecting member (236) couples the signal transfer region (222) to a reference voltage.

    19.
    发明专利
    未知

    公开(公告)号：DE10307822A1

    公开(公告)日：2003-11-06

    申请号：DE10307822

    申请日：2003-02-24

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

    IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

    Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

    STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS
    20.
    发明申请
    STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS 审中-公开
    用于SOC应用的高密度，基于TRENCH的非易失性随机接入SONOS存储器细胞的构造和方法

    公开(公告)号：WO2006110781A3

    公开(公告)日：2007-04-19

    申请号：PCT/US2006013561

    申请日：2006-04-12

    Applicant: IBM ,  MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

    Inventor： MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

    Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

    Abstract translation: 本发明提供了具有随机访问的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。在一个实施例中，2-Tr SONOS 提供了选择晶体管位于具有1至2μm的沟槽深度的沟槽结构内的单元，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

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