公开(公告)号：WO02054405A2

公开(公告)日：2002-07-11

申请号：PCT/US0147378

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/12 ,  G11C

CPC classification number: G11C7/12

Abstract: A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.

Abstract translation: 描述了具有电可控位线长度的位线的位线架构。 根据执行存储器访问的需要，位线提供有选择性地耦合或去耦合位线的局部位线段的开关。 位线长度可控的位线可以降低功耗，无需额外的读出放大器或额外的金属层。

公开(公告)号：WO0229972A2

公开(公告)日：2002-04-11

申请号：PCT/US0129192

申请日：2001-09-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MUELLER GERHARD ,  HANSON DAVID R

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521

Abstract: A buffer circuit that operates with reduced voltage input and output signals is described. The buffer circuit receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is form 0 volts to VRED, where VRED is less than VCC, the voltage used to operate most of the logic in the integrated circuit. The use of a buffer circuit that receives and generates signals with a reduced voltage range advantageously reduces power consumption.

Abstract translation: 描述了以降低的电压输入和输出信号操作的缓冲电路。 缓冲电路接收具有降低的电压范围的输入信号，并产生具有降低的电压范围的输出信号。 降低的电压范围为0伏至VRED，其中VRED小于VCC，用于操作集成电路中大部分逻辑的电压。 使用接收和产生具有降低的电压范围的信号的缓冲电路有利地降低功耗。

公开(公告)号：JP2001189080A

公开(公告)日：2001-07-10

申请号：JP37570099

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C11/409 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To reduce size of a sense amplifier without degrading capability or functionality of a sense amplifier. SOLUTION: This device has a latch coupled to a first bit line and a second bit line, and a driver having an input side and an output side connected to the latch, this driver is operated so that an active input signal activating this driver is received, over-drive voltage is increased by this active input signal, and the driver is operated with an amplified over-drive mode.

公开(公告)号：DE60035630D1

公开(公告)日：2007-09-06

申请号：DE60035630

申请日：2000-01-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

公开(公告)号：DE60137370D1

公开(公告)日：2009-02-26

申请号：DE60137370

申请日：2001-09-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MUELLER GERHARD ,  HANSON DAVID R

IPC: H03K19/00 ,  H03K19/0185

公开(公告)号：DE60016987D1

公开(公告)日：2005-02-03

申请号：DE60016987

申请日：2000-01-27

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID RUSSELL ,  MUELLER GERHARD

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417 ,  H03K5/00 ,  H04L7/00 ,  H04L7/02 ,  H04L25/40 ,  H03K19/00

Abstract: A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first voltage level higher than the reduced voltage level. The synchronized data capture circuit includes a timing driver circuit arranged to receive the timing signal. The timing driver circuit outputs a reduced voltage timing signal having the reduced voltage level. There is included a data driver circuit arranged to receive the data signal and the timing signal, the data driver outputting a reduced voltage clocked data signal having the reduced voltage level. There is further included a data clocking circuit coupled to the timing driver circuit and the data driver circuit. The data clocking circuit is arranged to receive the reduced voltage timing signal and the reduced voltage clocked data signal. The data clocking circuit outputs a synchronized capture data signal having the first voltage level higher than the reduced voltage level.

公开(公告)号：WO0201703A2

公开(公告)日：2002-01-03

申请号：PCT/US0120407

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： WEINFURTNER OLIVER ,  MUELLER GERHARD

IPC: G11C5/14 ,  G11C17/18 ,  H02M3/00

CPC classification number: G11C17/18 ,  G11C5/145

Abstract: A voltage pump system for programming fuses on a semiconductor chip, in accordance with the present invention, includes a first pump system (12) employing a supply voltage (VDD) of the semiconductor chip as an input. The first pump system supplies an output voltage (VPP) higher than the supply voltage on a first output line (16) without raising the supply voltage of the semiconductor chip. A second pump system (20) includes an input connected to the first output. The second pump system supplies an output voltage (VFuse) sufficient for programming electrical fuses on the semiconductor chip.

Abstract translation: 根据本发明的用于在半导体芯片上编程熔丝的电压泵系统包括采用半导体芯片的电源电压（VDD）作为输入的第一泵系统（12）。 第一泵系统在不提高半导体芯片的电源电压的情况下提供高于第一输出线（16）上的电源电压的输出电压（VPP）。 第二泵系统（20）包括连接到第一输出的输入。 第二个泵系统提供足以在半导体芯片上编程电气保险丝的输出电压（VFuse）。

公开(公告)号：WO0126139A3

公开(公告)日：2001-10-18

申请号：PCT/US0027216

申请日：2000-10-02

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SCHNABEL RAINER FLORIAN ,  GRUENING ULRIKE ,  RUPP THOMAS ,  MUELLER GERHARD

IPC: G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/10885 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/28525 ,  H01L21/76807 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10888 ,  H01L27/10894

Abstract: A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention, includes forming gate structures (204) for transistors in an array region (212) and a support region (214) of a substrate (202). First contacts (222) are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts (232) are formed between first level bitlines (234) in the array region and a first portion of the first contacts, while forming second contacts (236 and 260) to a first metal layer (233, 264) from the gate structures (204) and diffusion regions (262) in the support region. Third contacts (246) are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer (251, 268) from the first metal layer in the support region.

Abstract translation: 根据本发明，制造具有由三个接触电平构成的分裂电平折叠位线结构的半导体存储器的方法包括：在阵列区域（212）和支撑区域（214）中形成用于晶体管的栅极结构（204） 的衬底（202）。 第一触点（222）形成在阵列区域中的栅极结构之间的扩散区域。 第一触点具有与阵列区域中的所有第一触点基本相同的高度。 第二触点（232）形成在阵列区域中的第一级位线（234）和第一触点的第一部分之间，同时从栅极结构形成第二触点（236和260）到第一金属层（233,264） （204）和扩散区（262）。 第三触点（246）形成在阵列区域中的第二电平位线和第一触点的第二部分之间，同时从支撑区域中的第一金属层形成第三触点到第二金属层（251,268）。

公开(公告)号：WO0199194A2

公开(公告)日：2001-12-27

申请号：PCT/US0119242

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： REITHINGER MANFRED ,  KILLIAN MIKE ,  FRANKOWSKY GERD ,  TERLETZKI HARTMUND ,  STAHL ERNST ,  KIEHL OLIVER ,  VOGELSANG THOMAS ,  MUELLER GERHARD

IPC: H01L21/8242 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18 ,  H01L27/105 ,  H01L27/10 ,  H01L21/78 ,  H01L23/528

CPC classification number: H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

Abstract translation: 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的部分部分中的区域分开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触点，以将这种多个芯片与穿过晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：WO0199188A3

公开(公告)日：2003-04-24

申请号：PCT/US0119438

申请日：2001-06-18

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： REITHINGER MANFRED ,  MUELLER GERHARD ,  KILLIAN MIKE ,  STAHL ERNST ,  FRANKOWSKY GERD ,  TERLETZKI HARTMUND ,  KIEHL OLIVER ,  VOGELSANG THOMAS

IPC: H01L23/50 ,  H01L23/538 ,  H01L25/18 ,  H01L23/498 ,  H01L27/10

CPC classification number: H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer 76having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

Abstract translation: 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括在其上具有多个集成电路芯片的半导体晶片76的分数部分，这些芯片由晶片的部分部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。