公开(公告)号：WO0137325A2

公开(公告)日：2001-05-25

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8 2

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2-30sccm的C 4 F 8，20-80sccm的CO，2-30sccm的O> 2和50-400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：WO0245130A3

公开(公告)日：2004-01-08

申请号：PCT/US0144625

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L27/10 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10864 ,  H01L27/10885 ,  H01L27/10891

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.

Abstract translation: 一种用于生产非常高密度的嵌入式DRAM /非常高性能的逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元，包括：在硅衬底中形成法兰电容器， 栅极氧化物层，多晶硅层和沉积在其上的顶部侧面氮化物层; 在阵列和支撑区域上施加图案化掩模并在氮化物层，多晶硅层和浅沟槽隔离区域中形成凹陷; 在氮化物层，多晶硅层和浅沟槽隔离区域的凹槽中形成硅化物和氧化物盖; 施加阻挡掩模以保护支撑物，同时从阵列剥离氮化物层并将暴露的多晶硅层蚀刻到栅极氧化物层的顶部; 从支撑区域剥离氮化物层并在阵列和支撑区域上沉积多晶硅层; 应用掩模来图案化并在阵列中形成位线扩散螺柱着陆焊盘，并在支撑晶体管上形成栅极导体; 打击着陆板和门导体的顶部; 施加层间氧化层，然后在层间氧化层中开通通孔，以建立导电布线通道。

公开(公告)号：WO0118863A9

公开(公告)日：2002-11-07

申请号：PCT/US0024402

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BRINTZINGER AXEL ,  GAMBINO JEFFREY ,  RUPP THOMAS ,  HALLE SCOTT

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to form a cavity for a fusible link in a semiconductor device, an etchable material is applied over and around a portion of the fusible link and the etchable material is coated with a protection layer. The access abutting the etchable material is formed through the protection layer. After the removal of the etchable material, the access is partially filled with a refilling material to thereby form the cavity.

Abstract translation: 为了在半导体器件中形成用于可熔连接件的空腔，可蚀刻材料施加在可熔连接件的一部分上和周围，并且可蚀刻材料被涂覆有保护层。 通过保护层形成邻接可蚀刻材料的通路。 在去除可蚀刻材料之后，进入部分地填充有填充材料，从而形成空腔。

公开(公告)号：WO0137325A9

公开(公告)日：2002-07-04

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8, 20 - 80sccm of CO, 2 - 30sccm of O2 and 50 - 400sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2 - 30sccm的C4F8，20 - 80sccm的CO，2 - 30sccm的O2和50 - 400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：WO0126139A3

公开(公告)日：2001-10-18

申请号：PCT/US0027216

申请日：2000-10-02

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SCHNABEL RAINER FLORIAN ,  GRUENING ULRIKE ,  RUPP THOMAS ,  MUELLER GERHARD

IPC: G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/10885 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/28525 ,  H01L21/76807 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10888 ,  H01L27/10894

Abstract: A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention, includes forming gate structures (204) for transistors in an array region (212) and a support region (214) of a substrate (202). First contacts (222) are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts (232) are formed between first level bitlines (234) in the array region and a first portion of the first contacts, while forming second contacts (236 and 260) to a first metal layer (233, 264) from the gate structures (204) and diffusion regions (262) in the support region. Third contacts (246) are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer (251, 268) from the first metal layer in the support region.

Abstract translation: 根据本发明，制造具有由三个接触电平构成的分裂电平折叠位线结构的半导体存储器的方法包括：在阵列区域（212）和支撑区域（214）中形成用于晶体管的栅极结构（204） 的衬底（202）。 第一触点（222）形成在阵列区域中的栅极结构之间的扩散区域。 第一触点具有与阵列区域中的所有第一触点基本相同的高度。 第二触点（232）形成在阵列区域中的第一级位线（234）和第一触点的第一部分之间，同时从栅极结构形成第二触点（236和260）到第一金属层（233,264） （204）和扩散区（262）。 第三触点（246）形成在阵列区域中的第二电平位线和第一触点的第二部分之间，同时从支撑区域中的第一金属层形成第三触点到第二金属层（251,268）。

公开(公告)号：DE60129605D1

公开(公告)日：2007-09-06

申请号：DE60129605

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L21/00 ,  H01L27/10 ,  H01L21/8242

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.