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    11.
    发明专利
    未知

    公开(公告)号：DE69624312T2

    公开(公告)日：2003-06-18

    申请号：DE69624312

    申请日：1996-08-12

    Applicant: IBM

    Inventor： DEBROSSE JOHN KENNETH ,  KIRIHATA TOSHIAKI ,  WONG HING

    IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C29/50 ,  G11C29/00

    Abstract: A bit line pair is coupled through a pair of high-resistance pass gates (164L,164R) to a sense amp (166). During sense, the high-resistance pass gates (164L,164R) act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp (166). A control circuit (185) selectively switches on and off bit line equalisation coincident with selectively passing either the equalisation voltage or set voltages to the sense amp (166) and an active sense amp load (172,174). Further, after it is set, the sense amp (166) is selectively connected to LDLs (182,184) through low-resistance column select pass gates (178,180). Therefore, the sense amp (166) quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp (166) to a second sense amplifier and off chip. After data is passed to the LDLs (182,184), the control circuit (185) enables the active sense amp load (172,174) to pull the sense amp high side to a full up level. Additionally, because the control circuit (185) uses the equalisation voltage to disable the sense amp (166), cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. The cell signal may be selected to determine both a high and a low signal margin.

    15.
    发明专利
    未知

    公开(公告)号：DE69834540T2

    公开(公告)日：2007-05-03

    申请号：DE69834540

    申请日：1998-12-18

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

    IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/408 ,  G11C11/409 ,  G11C16/06

    Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

    17.
    发明专利
    未知

    公开(公告)号：DE69718609D1

    公开(公告)日：2003-02-27

    申请号：DE69718609

    申请日：1997-11-25

    Applicant: IBM

    Inventor： DEBROSSE JOHN ,  KIRIHATA TOSHIAKI ,  WONG HING

    IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108 ,  G06F11/20

    Abstract: Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.

    19.
    发明专利
    未知

    公开(公告)号：DE69618857T2

    公开(公告)日：2002-09-12

    申请号：DE69618857

    申请日：1996-05-31

    Applicant: IBM

    Inventor： KIRIHATA TOSHIAKI ,  WONG HING

    IPC: G11C29/12 ,  G11C29/06 ,  G11C29/10 ,  G11C29/00

    Abstract: A method of testing a RAM. The RAM array is arranged in rows and columns. The rows are grouped into word line groups. The method includes the steps of: a) asserting an array select signal; b) selecting a group of rows in the array; c) selecting at least one row of the selected group of rows; and, d) repeating steps b and c until all of the groups are selected. Array Sense Amps may be set when the first group is selected and remain set until the last group is selected. In one test, word lines in all of the selected rows are activated and remain activated until the final selected row is selected. In a second test, word lines in selected groups are toggled with RAS. If a group contains a known defective word line, that group is either not addressed or its selection is disabled. In each selected group, one row, alternating rows or, all of the rows may be selected.

    20.
    发明专利
    未知

    公开(公告)号：DE69618857D1

    公开(公告)日：2002-03-14

    申请号：DE69618857

    申请日：1996-05-31

    Applicant: IBM

    Inventor： KIRIHATA TOSHIAKI ,  WONG HING

    IPC: G11C29/12 ,  G11C29/06 ,  G11C29/10 ,  G11C29/00

    Abstract: A method of testing a RAM. The RAM array is arranged in rows and columns. The rows are grouped into word line groups. The method includes the steps of: a) asserting an array select signal; b) selecting a group of rows in the array; c) selecting at least one row of the selected group of rows; and, d) repeating steps b and c until all of the groups are selected. Array Sense Amps may be set when the first group is selected and remain set until the last group is selected. In one test, word lines in all of the selected rows are activated and remain activated until the final selected row is selected. In a second test, word lines in selected groups are toggled with RAS. If a group contains a known defective word line, that group is either not addressed or its selection is disabled. In each selected group, one row, alternating rows or, all of the rows may be selected.

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