公开(公告)号：US09306003B2

公开(公告)日：2016-04-05

申请号：US14396709

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract translation: 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

公开(公告)号：US20150294879A1

公开(公告)日：2015-10-15

申请号：US14442890

申请日：2012-12-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Jun Luo ,  Chunlong Li ,  Guilei Wang

IPC: H01L21/306 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/31053 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.

Abstract translation: 提供一种翅片结构的制造方法。 该方法可以包括在衬底上形成初始翅片，在衬底上形成电介质层以覆盖初始翅片，通过溅射对电介质层进行平面化，并进一步蚀刻介电层以暴露初始鳍片的一部分，其中 露出部分作为翅片。

公开(公告)号：US20140273426A1

公开(公告)日：2014-09-18

申请号：US14119869

申请日：2012-12-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/51

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/513 ,  H01L29/66545

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层，并修剪硬掩模层，使得修整的硬掩模层具有小于或等于22nm的宽度; 并根据修整的硬掩模层蚀刻顶层非晶硅，ONO结构的硬掩模和底层非晶硅，以及去除硬掩模层和顶层非晶硅。