公开(公告)号：WO2004030208A3

公开(公告)日：2004-07-22

申请号：PCT/US0329532

申请日：2003-09-17

Applicant: INTEL CORP

Inventor： WANG LI-PENG ,  MA QING ,  YANKOVICH ISRAEL ,  BUTLER RICHARD

IPC: H01L41/09 ,  H01L41/00 ,  H01L41/08 ,  H01L41/18 ,  H01L41/22 ,  H03H3/02 ,  H03H9/02 ,  H03H9/17

CPC classification number: H03H3/02 ,  H03H9/02133 ,  H03H9/174 ,  H03H2003/023 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A film bulk acoustic resonator formed on a substrate (710) includes a layer of piezoelectric material (735) having a first major surface, and a second major surface sandwiched between a first conductive (732) and a second conductive layer (736). The substrate on which the film bulk acoustic resonator is formed has an opening (750) therein which exposes the first conductive layer (732) of the film bulk acoustic resonator. The opening (750) is substantially in the shape of a parallelogram having a first pair of parallel sides (751, 752) and a second pair of parallel sides. One of the first pair of parallel sides makes an angle at other than 90 degrees with one of the second pair of parallel sides.

Abstract translation: 形成在基板（710）上的薄膜体声波谐振器包括具有第一主表面的压电材料层（735）和夹在第一导电层（732）和第二导电层（736）之间的第二主表面。 其上形成有膜体声波谐振器的基板在其中具有暴露膜体声波谐振器的第一导电层（732）的开口（750）。 开口（750）基本上为具有第一对平行边（751,752）和第二对平行边的平行四边形的形状。 第一对平行边之一与第二对平行边之一形成不同于90度的角度。

公开(公告)号：WO0223631A3

公开(公告)日：2002-06-06

申请号：PCT/US0128188

申请日：2001-09-07

Applicant: INTEL CORP ,  MA QING

Inventor： MA QING

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A packaging technology that fabricates a microelectronic package including build-up layers (118, 124, 136) having conductive traceses (124) on an encapsulated microelectronic die (102) and on other packaging material that surrounds the microelectronic die (112), wherein an moisture barrier structure is simultaneously formed with the conductive traces. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side. Packaging material(s) (112) is disposed adjacent the microelectronic die side (2), wherein the packaging material (112) includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer (118) may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive (124) trace is then formed on the first dielectric material layer to electrically contact the microelectronic die active surface. A barrier structure proximate an edge of the microelectronic package is formed simultaneously out of the same material as the conductive traces (124).

Abstract translation: 一种制造微电子封装的封装技术，包括在封装的微电子管芯（102）上以及围绕微电子管芯（112）的其它封装材料上具有导电迹线（124）的堆积层（118,124,136），其中 与导电迹线同时形成防潮结构。 示例性的微电子封装包括具有活性表面和至少一个侧面的微电子管芯。 包装材料（112）被设置在微电子管芯侧面（2）附近，其中包装材料（112）包括至少一个与微电子管芯有效表面平面的表面。 第一介电材料层（118）可以设置在微电子管芯有源表面和封装材料表面的至少一部分上。 然后在第一介电材料层上形成至少一个导电（124）迹线以电接触微电子管芯有源表面。 靠近微电子封装的边缘的阻挡结构与导电迹线（124）相同的材料同时形成。

公开(公告)号：WO2011126925A2

公开(公告)日：2011-10-13

申请号：PCT/US2011030808

申请日：2011-03-31

Applicant: INTEL CORP ,  MA QING ,  HE JUN ,  MORROW PATRICK ,  FISCHER PAUL B ,  BALAKRISHNAN SRIDHAR ,  RADHAKRISHNAN SATISH ,  ANDRYUSHCHENKO TATYANA TANYA ,  XU GUANGHAI

Inventor： MA QING ,  HE JUN ,  MORROW PATRICK ,  FISCHER PAUL B ,  BALAKRISHNAN SRIDHAR ,  RADHAKRISHNAN SATISH ,  ANDRYUSHCHENKO TATYANA TANYA ,  XU GUANGHAI

IPC: H05K3/32 ,  H05K1/18

CPC classification number: H01L24/19 ,  B23K1/0016 ,  H01L21/0334 ,  H01L24/11 ,  H01L2224/245 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/4015 ,  H05K2201/1028 ,  H01L2924/00

Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Abstract translation: 本主题涉及制造微电子器件的领域。 在至少一个实施例中，本主题涉及形成具有其部分的互连，其在附接到外部设备之后在冷却期间从微电子器件脱粘。 脱粘部分允许互连件弯曲并吸收应力。

公开(公告)号：WO2007005701A2

公开(公告)日：2007-01-11

申请号：PCT/US2006025755

申请日：2006-06-29

Applicant: INTEL CORP ,  MA QING ,  WANG LI-PENG ,  RAO VALLURI

Inventor： MA QING ,  WANG LI-PENG ,  RAO VALLURI

CPC classification number: G01N29/022 ,  G01N29/036 ,  G01N33/54373 ,  G01N2291/021 ,  G01N2291/0255 ,  G01N2291/0256 ,  G01N2291/0426 ,  G01N2291/106

Abstract: An FBAR device may be chemically functionalized by depositing an interactive layer so that targeted chemicals are preferentially adsorbed. Such miniaturized chemical sensors may be combined with wireless network technology. For example, a chemical sensor may be integrated in a cell phone, PDA, a watch, or a car with wireless connection and GPS. Since such devices are widely populated, a national sensor network may be established. Consequently, a national toxicity map can be generated in real time. Detailed chemical information may be obtained, such as if a chemical is released by a source fixed on ground or by a moving object, or if is spread by explosives or by wind and so on.

Abstract translation: FBAR器件可以通过沉积交互层进行化学功能化，从而优先吸附目标化学物质。 这种小型化学传感器可以与无线网络技术组合。 例如，化学传感器可以集成在具有无线连接和GPS的手机，PDA，手表或汽车中。 由于这样的设备被广泛地填充，所以可以建立国家传感器网络。 因此，可以实时生成国家毒性图。 可以获得详细的化学信息，例如化学品被固定在地面上的源或被移动的物体释放，或者如果被爆炸物或风等传播。

公开(公告)号：WO0227788A2

公开(公告)日：2002-04-04

申请号：PCT/US0130157

申请日：2001-09-25

Applicant: INTEL CORP ,  MA QING ,  MAVEETY JAMES ,  TRAN QUAN

Inventor： MA QING ,  MAVEETY JAMES ,  TRAN QUAN

IPC: H01L23/36 ,  H01L23/367

CPC classification number: H01L23/36 ,  H01L23/3677 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/16151 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A microelectronic die is aligned with a package substrate and attached to it using solder balls. A specially shaped heat spreader, preferably with a coefficient of thermal expansion (CTE) similar to that of silicon, is attached to the back side of the die using a heat-conducting adhesive. An epoxy-based material is flowed into the gap between the die, the substrate, and the heat spreader via a through-hole in either the substrate or the heat spreader using a dispense process or a transfer molding process. By positioning the heat spreader to abut the die corners and/or edges, the stresses on the die are substantially reduced or eliminated.

Abstract translation: 微电子管芯与封装衬底对准并使用焊球附着于其上。 使用导热粘合剂将特定形状的散热器（优选地具有与硅的热膨胀系数（CTE）相似的热膨胀系数（CTE））附接到管芯的背面。 使用分配过程或传递模塑过程，基于环氧树脂的材料经由基板或散热器中的通孔流入管芯，基板和散热器之间的间隙中。 通过将散热器定位成邻接模具拐角和/或边缘，模具上的应力被显着减小或消除。

公开(公告)号：WO0215266A2

公开(公告)日：2002-02-21

申请号：PCT/US0125060

申请日：2001-08-10

Applicant: INTEL CORP

Inventor： MU XIAO-CHUN ,  MA QING ,  FUJIMOTO HARRY

IPC: H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends adjacent the microelectronic die active surface and adjacent the encapsulation material surface.

Abstract translation: 一种微电子封装，其包括具有活性表面和至少一个侧面的微电子管芯。 封装材料邻近微电子管芯侧设置，其中封装材料包括至少一个与微电子管芯有效表面平面的表面。 第一介电材料层可以设置在微电子管芯有源表面和封装材料表面的至少一部分上。 然后至少一个导电迹线设置在第一介电材料层上。 导电迹线与微电子管芯有源表面电接触。 至少一个导电迹线在微电子管芯有源表面附近延伸并与封装材料表面相邻。

公开(公告)号：WO2011084216A3

公开(公告)日：2011-09-09

申请号：PCT/US2010054931

申请日：2010-11-01

Applicant: INTEL CORP ,  MA QING ,  HU CHUAN ,  MORROW PATRICK

Inventor： MA QING ,  HU CHUAN ,  MORROW PATRICK

IPC: H01L23/485 ,  H05K3/46

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）器件的衬底的实施例。 衬底包括由两个或更多个已经粘合在一起的分立的玻璃层组成的芯。 单独的结合层可以设置在相邻的玻璃层之间以将这些层结合在一起。 衬底还可以包括在多层玻璃芯的相对侧上的堆积结构，或者可能在芯的一侧上。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸穿过多层玻璃芯，并且一个或多个导体可以与设置在芯上的积层结构电耦合。 描述并要求保护其他实施例。

公开(公告)号：WO2004000718A2

公开(公告)日：2003-12-31

申请号：PCT/US0318306

申请日：2003-06-10

Applicant: INTEL CORP

Inventor： MA QING ,  CHOU TSUNG-KUAN

IPC: B81C1/00 ,  B81B7/00 ,  B81B7/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L23/66 ,  H01L27/04

CPC classification number: H01L23/66 ,  B81B7/0006 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductive bridge (16) in a second conductive layer may be utilized to join a pair of spaced apart conductive strips (12) in a first conductive layer. A gap (44) between the first and second strips (12) may be bridged by the bridge (16) while isolating both the 5 first and second strips (12) and the bridge (16) itself from another conductor (18) which extends through the gap (44) between the first and second strips (12).

Abstract translation: 可以使用第二导电层中的导电桥（16）将第一导电层中的一对间隔开的导电条（12）连接起来。 第一和第二条带（12）之间的间隙（44）可以由桥接器（16）桥接，同时将第一和第二条带（12）和桥接件（16）本身与另一个延伸的导体（18）隔离 通过第一和第二条带（12）之间的间隙（44）。

公开(公告)号：WO02052592A3

公开(公告)日：2003-03-27

申请号：PCT/US0144454

申请日：2001-11-26

Applicant: INTEL CORP

Inventor： MA QING ,  RAO VALLURI R ,  CHENG PENG

IPC: H01G5/38 ,  B81B3/00 ,  H01G5/00 ,  H01G5/16 ,  H01L21/20

CPC classification number: H01G5/16 ,  H01G5/40 ,  Y10T307/724 ,  Y10T307/729

Abstract: The present invention relates to a stepped micro electromechanical structure (MEMS) capacitor that is actuated by a plurality of MEMS switches may be within the stepped capacitor circuit, or they may be actuated by an independent circuit. The stepped capacitor may also be varied with intermediate steps of capacitance by providing at least one variable capacitor in the stepped MEMS capacitor structure.

Abstract translation: 本发明涉及由多个MEMS开关驱动的阶梯式微机电结构（MEMS）电容器，其可以在阶梯式电容器电路内，或者它们可由独立电路驱动。 通过在阶梯式MEMS电容器结构中提供至少一个可变电容器，阶梯式电容器也可以随着电容的中间步骤而变化。

公开(公告)号：WO2011084235A3

公开(公告)日：2011-09-09

申请号：PCT/US2010056310

申请日：2010-11-11

Applicant: INTEL CORP ,  MA QING ,  RAO VALLURI R ,  TRAN QUAN A ,  SANKMAN ROBERT L ,  SWAN JOHANNA M

Inventor： MA QING ,  RAO VALLURI R ,  TRAN QUAN A ,  SANKMAN ROBERT L ,  SWAN JOHANNA M

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H05K1/112 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/15 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K3/0014 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10287 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0108 ,  H05K2203/0228 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的玻璃芯基板的实施例。 玻璃芯基板包括玻璃芯和在玻璃芯的相对侧上的堆积结构。 导电端子可以形成在玻璃芯基板的两侧。 IC管芯可以与衬底的一侧上的端子耦合，而相对侧上的端子可以与诸如电路板的下一级组件耦合。 玻璃芯可以包括其中已经形成有导体的单片玻璃，或者玻璃芯可以包括已经接合在一起的两个或更多个玻璃部分，每个部分具有导体。 导体延伸穿过玻璃芯，并且一个或多个导体可以与布置在玻璃芯上的积层结构电耦合。 描述并要求保护其他实施例。