公开(公告)号：JP2004312028A

公开(公告)日：2004-11-04

申请号：JP2004146040

申请日：2004-05-17

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： MU XIAO-CHUN ,  SIVARAM SRINIVASAN ,  GARDNER DONALD S ,  FRASER DAVID B

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To form an interconnect portion within a predetermined channel of a semiconductor device in which the depth of an interconnect channel can be easily controlled. SOLUTION: A method of forming the interconnect portion on the semiconductor substrate has a process for forming a silicon nitride layer 23 on the semiconductor substrate, a process for forming a first opening in the silicon nitride layer, a process for filling up the first opening with a conductive plug 41, a process for forming a dielectric layer 50 on the silicon nitride layer and the conductive plug, and a process for forming the interconnect portion 61 so that the interconnect portion exists on the dielectric layer, and at least a part of which exists on the conductive plug 41 and the silicon nitride layer 23. Further, the method has a process for removing the dielectric layer after forming the interconnect portion, and a process for forming a passive layer 80 on the interconnect portion, and surrounding the interconnect portion 61 with the silicon nitride layer 23, the conductive plug 41 and the passive layer 80. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：WO0215266A2

公开(公告)日：2002-02-21

申请号：PCT/US0125060

申请日：2001-08-10

Applicant: INTEL CORP

Inventor： MU XIAO-CHUN ,  MA QING ,  FUJIMOTO HARRY

IPC: H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends adjacent the microelectronic die active surface and adjacent the encapsulation material surface.

Abstract translation: 一种微电子封装，其包括具有活性表面和至少一个侧面的微电子管芯。 封装材料邻近微电子管芯侧设置，其中封装材料包括至少一个与微电子管芯有效表面平面的表面。 第一介电材料层可以设置在微电子管芯有源表面和封装材料表面的至少一部分上。 然后至少一个导电迹线设置在第一介电材料层上。 导电迹线与微电子管芯有源表面电接触。 至少一个导电迹线在微电子管芯有源表面附近延伸并与封装材料表面相邻。

公开(公告)号：WO0117013A3

公开(公告)日：2001-10-25

申请号：PCT/US0040681

申请日：2000-08-18

Applicant: INTEL CORP ,  LI JIAN ,  MU XIAO CHUN ,  BALAKRISHNAN SRIDHAR

Inventor： LI JIAN ,  MU XIAO-CHUN ,  BALAKRISHNAN SRIDHAR

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/285

CPC classification number: H01L23/485 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  Y10T428/12479 ,  Y10T428/12556 ,  Y10T428/12583 ,  Y10T428/12743 ,  Y10T428/12812 ,  Y10T428/31678 ,  H01L2224/05552

Abstract: Methods and apparatuses are disclosed for forming an under bump metallizaton structure that includes a refractory hydride layer. The refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350 DEG C approximately 550 DEG C.

Abstract translation: 公开了用于形成包括耐火氢化物层的凸块下金属化结构的方法和装置。 耐火层在快速热处理期间形成，其中环境氢被用于热处理室中。 快速热处理可以在约350℃至约550℃的温度下进行。

公开(公告)号：WO0221595A3

公开(公告)日：2003-08-14

申请号：PCT/US0126949

申请日：2001-08-29

Applicant: INTEL CORP

Inventor： HENAO MARIA ,  MU XIAO-CHUN ,  MA QING ,  VU QUAT ,  LI JIAN

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L23/532 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  Y10T29/4935 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

Abstract translation: 一种微电子封装，包括设置在微电子封装芯中的开口内的微电子管芯，其中封装材料设置在不被微电子管芯占据的开口部分内。 然后在微电子管芯，密封剂材料和微电子封装芯上制造介电材料和导电迹线的堆叠层以形成微电子封装。

公开(公告)号：WO0247162A3

公开(公告)日：2003-08-07

申请号：PCT/US0149898

申请日：2001-11-09

Applicant: INTEL CORP ,  HENAO MARIA V ,  MU XIAO-CHUN ,  MA QING ,  VU QUAT T ,  TOWLE STEVEN N

Inventor： HENAO MARIA V ,  MU XIAO-CHUN ,  MA QING ,  VU QUAT T ,  TOWLE STEVEN N

IPC: H01L23/12 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/433 ,  H01L23/538 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package fabrication technology that attaches at least one microelectronic die onto a heat spreader and encepsulates the microelectronic die/dice thereon which may further include a microelectronic packaging core abutting the heat spreader wherein the microelectronic die/dice reside within at least one opening in a microelectronic package core. After encapsulation, build-up layers may be fabricated to form electrical connections with the microelectronic die/dice.

Abstract translation: 一种微电子封装制造技术，其将至少一个微电子管芯附接到散热器上并嵌入其上的微电子管芯/裸片，其可进一步包括邻接散热器的微电子封装芯，其中微电子管芯/裸片位于至少一个开口中 微电子封装核心。 在封装之后，可以制造堆积层以形成与微电子管芯/裸片的电连接。

公开(公告)号：AT429032T

公开(公告)日：2009-05-15

申请号：AT01962043

申请日：2001-08-10

Applicant: INTEL CORP

Inventor： MU XIAO-CHUN ,  MA QING ,  FUJIMOTO HARRY

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46

公开(公告)号：GB2370417B

公开(公告)日：2004-03-31

申请号：GB0206843

申请日：2000-08-18

Applicant: INTEL CORP

Inventor： LI JIAN ,  MU XIAO-CHUN ,  BALAKRISHNAN SRIDHAR

IPC: H01L21/60 ,  H01L23/485

公开(公告)号：AU2002345992A1

公开(公告)日：2003-03-03

申请号：AU2002345992

申请日：2002-06-28

Applicant: INTEL CORP

Inventor： MU XIAO-CHUN ,  ISENBERGER MARK ,  LI JIAN

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  G11C11/22 ,  H01L21/64

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

公开(公告)号：DE10296984T5

公开(公告)日：2004-10-14

申请号：DE10296984

申请日：2002-06-28

Applicant: INTEL CORP

Inventor： ISENBERGER MARK ,  MU XIAO-CHUN ,  LI JIAN

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  G11C11/22 ,  H01L21/64

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

公开(公告)号：HK1055844A1

公开(公告)日：2004-01-21

申请号：HK03108126

申请日：2003-11-10

Applicant: INTEL CORP

Inventor： MU XIAO-CHUN ,  MA QING ,  FUJIMOTO HARRY

IPC: H01L20090101 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46