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    11.
    发明专利
    未知

    公开(公告)号：DE69530788D1

    公开(公告)日：2003-06-18

    申请号：DE69530788

    申请日：1995-12-06

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES ,  CHO SOO ,  PETERSON B ,  LANE R ,  JOSHI M ,  SONGER NEIL

    IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

    Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

    Serial interrupt bus protocol
    14.
    发明专利
    Serial interrupt bus protocol 未知

    公开(公告)号：AU4416496A

    公开(公告)日：1996-06-26

    申请号：AU4416496

    申请日：1995-12-06

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES ,  CHO SUNG SOO ,  PETERSON NICHOLAS B ,  LANE THOMAS R ,  JOSHI JAYESH M ,  SONGER NEIL

    IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

    Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

    Berichten der Dienstlatenzzeit eines Downstream-Gerätes für Power Management
    15.
    发明专利
    Berichten der Dienstlatenzzeit eines Downstream-Gerätes für Power Management 未知

    公开(公告)号：DE102009060269B4

    公开(公告)日：2014-10-16

    申请号：DE102009060269

    申请日：2009-12-23

    Applicant: INTEL CORP

    Inventor： JEYASEELAN JAYA ,  WALSH JIM ,  GOUGH ROBERT ,  COOPER BARNES ,  SONGER NEIL

    IPC: G06F1/32 ,  G06F13/00 ,  G06F13/38

    Abstract: Vorrichtung, umfassend: erste Logik, um einen Übergang für zumindest einen Teil eines Downstream-Gerätes von einem ersten Zustand in einen zweiten, unterschiedlichen Zustand zu identifizieren, wobei die ersten und zweiten Zustände unterschiedlichen Leveln entsprechen, die die Aktivität für zumindest einen Teil des Downstream-Gerätes betreffen; und zweite Logik, um einer Dienstlatenzzeit entsprechende Daten an ein Upstream-Gerät zu übertragen, wobei die Daten die Dienstlatenzzeit berichten und in Antwort auf eine Ermittlung, dass der zweite Zustand ein niedriger aktiver Zustand ist und eine Dauer des zweiten Zustands eine vorher festgelegte Zeitspanne überschreitet, übertragen werden sollen, und der identifizierte Übergang zur Verwendung durch ein oder mehr Upstream-Geräte dient, um Energie auf einer Plattform zumindest teilweise basierend auf der Dienstlatenzzeit zu regeln, wobei die Plattform die Downstream- und Upstream- Geräte umfasst und Geräte der Plattform über einen oder mehrere Links der Plattform miteinander kommunikativ gekoppelt sind.

    Generating a power management policy for components of a system based on data from other components
    16.
    发明专利
    Generating a power management policy for components of a system based on data from other components 未知

    公开(公告)号：GB2458805A

    公开(公告)日：2009-10-07

    申请号：GB0905585

    申请日：2009-03-31

    Applicant: INTEL CORP

    Inventor： JEYASEELAN JAYA L ,  SONGER NEIL ,  COOPER BARNES ,  DIEFENBAUGH PAUL S

    IPC: G06F1/32

    Abstract: A power management controller 15 receives power management guidelines 30...36 from a first set of components 20...26 and uses them to develop a power management policy 50 for a second set of components 60...66. The guidelines may include latency parameters, such as latency tolerances, for the first set of components. The controller may determine a sleep level for the second set of components. The sleep levels for the second set of components may be selected such that the wake-up times of the sleep levels match the latency tolerances of the first set of components. The power management controller may also use activity or traffic patterns to determine the power management policy.

    17.
    发明专利
    未知

    公开(公告)号：DE69732181T2

    公开(公告)日：2005-12-29

    申请号：DE69732181

    申请日：1997-05-27

    Applicant: INTEL CORP

    Inventor： REINHARDT DENNIS ,  KARDACH P ,  HORIGAN W ,  SONGER NEIL ,  GLEW F

    IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10 ,  G06F9/46

    Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.

    20.
    发明专利
    未知

    公开(公告)号：BR9508427A

    公开(公告)日：1997-11-25

    申请号：BR9508427

    申请日：1995-12-06

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES ,  CHO SUNG SOO ,  PETERSON NICHOLAS B ,  LANE THOMAS R ,  JOSHI JAYESH M ,  SONGER NEIL

    IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

    Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

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