公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20240105576A1

公开(公告)日：2024-03-28

申请号：US17953210

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Kyle MCELHINNY ,  Xiaoying GUO ,  Hiroki TANAKA ,  Haobo CHEN

IPC: H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core and a pad over the core. In an embodiment, a solder resist is over the pad, and an opening into the solder resist exposes a portion of the pad. In an embodiment, the package substrate further comprises a surface finish over the pad and within the opening.

公开(公告)号：US20240105575A1

公开(公告)日：2024-03-28

申请号：US17953206

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Jason M. GAMBA ,  Haifa HARIRI ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Kyle MCELHINNY ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Haobo CHEN ,  Bai NIE ,  Numair AHMED

IPC: H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.

公开(公告)号：US20230093258A1

公开(公告)日：2023-03-23

申请号：US17482830

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Haobo CHEN ,  Leonel ARANA

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.

公开(公告)号：US20190206781A1

公开(公告)日：2019-07-04

申请号：US15859309

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Haobo CHEN ,  Changhua LIU ,  Sri Ranga Sai BOYAPATI ,  Bai NIE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822

Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20250106983A1

公开(公告)日：2025-03-27

申请号：US18373457

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Kyle ARRINGTON ,  Dingying David XU ,  Ziyin LIN ,  Timothy GOSSELIN ,  Elah BOZORG-GRAYELI ,  Aravindha ANTONISWAMY ,  Wei LI ,  Haobo CHEN ,  Yiqun BAI ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Ashay DANI

IPC: H05K1/02 ,  H05K1/03

Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.

公开(公告)号：US20240332125A1

公开(公告)日：2024-10-03

申请号：US18128848

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Clay ARRINGTON ,  Bohan SHAN ,  Haobo CHEN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying XU ,  Bai NIE

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/24 ,  H01L23/498

CPC classification number: H01L23/3737 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/24 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a first layer and a second layer over the first layer. In an embodiment, the second layer comprises a dielectric material including sulfur. In an embodiment, fillers are within the second layer. In an embodiment, the fillers have a volume fraction that is less than approximately 0.2.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20220196914A1

公开(公告)日：2022-06-23

申请号：US17131678

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Bai NIE ,  Haobo CHEN ,  Zhichao ZHANG ,  Sai VADLAMANI ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H01L23/48 ,  G02B6/02 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.

公开(公告)号：US20210028101A1

公开(公告)日：2021-01-28

申请号：US16522483

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Bai NIE ,  Haobo CHEN ,  Gang DUAN ,  Brandon C. MARIN ,  Srinivas PIETAMBARAM

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of making such packages. In an embodiment, a package substrate comprises a substrate comprising a first dielectric material, a first trace embedded in the substrate, and a patch in direct contact with the first trace. In an embodiment, the patch comprises a second dielectric material that is different than the first dielectric material.