公开(公告)号：US20190393191A1

公开(公告)日：2019-12-26

申请号：US16464213

申请日：2016-12-27

Applicant: Intel IP Corporation

Inventor： Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Bernd WAIDHAS ,  Thomas WAGNER

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768

Abstract: Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed.

公开(公告)号：US20190214369A1

公开(公告)日：2019-07-11

申请号：US16325970

申请日：2016-09-28

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Thomas WAGNER ,  Klaus REINGRUBER ,  Bernd WAIDHAS ,  Andreas WOLTER

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L29/0657 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

公开(公告)号：US20190206833A1

公开(公告)日：2019-07-04

申请号：US15772730

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Thorsten MEYER ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Christian GEISSLER ,  Sven ALBERS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/12 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/065 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.

公开(公告)号：US20180331070A1

公开(公告)日：2018-11-15

申请号：US15774906

申请日：2015-12-26

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US20160329272A1

公开(公告)日：2016-11-10

申请号：US14779967

申请日：2014-12-19

Applicant: Intel IP Corporation

Inventor： Christian GEISSLER ,  Georg SEIDEMANN ,  Klaus REINGRUBER

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L23/49827 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure describes embodiments of a stacked semiconductor device package and associated techniques and configurations. A package may include a packaging substrate having interconnects and a first semiconductor device attached to one side and a second semiconductor device attached to the opposite side. The devices may be attached in a flip chip configuration with pad sides facing each other on opposite sides of the substrate. The devices may be electrically coupled by the interconnects. The devices may be electrically coupled to fan out pads on the substrate. A dielectric layer may be coupled to the second side of the substrate and encapsulate the second device. Vias may route electrical signals from the fan out area through the dielectric layer and into a redistribution layer coupled to the dielectric layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开描述了堆叠的半导体器件封装和相关联的技术和配置的实施例。 封装可以包括具有互连的封装衬底和附接到一侧的第一半导体器件和附接到相对侧的第二半导体器件。 这些器件可以以倒装芯片配置附接，其中焊盘侧面在衬底的相对侧上彼此面对。 这些器件可以通过互连电耦合。 这些器件可以电耦合到扇出衬底上的焊盘。 电介质层可以耦合到衬底的第二侧并封装第二器件。 通孔可以将来自风扇输出区域的电信号通过电介质层和耦合到电介质层的再分布层布置。 可以描述和/或要求保护其他实施例。