公开(公告)号：DE19650493A1

公开(公告)日：1997-06-26

申请号：DE19650493

申请日：1996-12-05

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  CHO DEOK-HO ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  PYUN KWANG-EUI

IPC: H01L21/331 ,  H01L29/737 ,  H01L29/73 ,  H01L21/76

Abstract: The transistor includes a semiconductor substrate, e.g. of silicon, with a buried collector and having an oxide film with a conductive, thin-film base electrode formed on the substrate one after another. The substrate is provided with a heterojunction of e.g. Si or SiGe Ge. The collector is surrounded by the conductive thin film and is formed in transistor active region, bounded by patterns of the conductive thin and first oxide films on the buried collector on both sides of the conductive thin film is formed a first spacing layer. A multilayer base is formed in the active region, while an emitter is grown selectively on the base in an emitter region, bounded by etching of a second oxide film, on whose both sides is formed a second spacing layer. The emitter carries an electrode, while a passivating insulation layer is formed on the structure surface. Metal coupling lines are formed on the base, emitter, and buried collector and go back through the insulation passivation layer and/or the two oxide layers.

公开(公告)号：DE4444776A1

公开(公告)日：1996-06-27

申请号：DE4444776

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L29/735

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

公开(公告)号：GB2296375A

公开(公告)日：1996-06-26

申请号：GB9425590

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  CHO DEOK-HO ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  KWON OH-JOON

IPC: H01L21/331 ,  H01L29/737

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is reduced by using a metallic silicide as the base (25), comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region (21); growing a collector epitaxial layer (22) on the buried collector region and forming a field oxide layer (23); selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer (25) and a first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film (26) thereon to form a base electrode thin film; forming a capping oxide layer (27), forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask, removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.

公开(公告)号：GB2296129B

公开(公告)日：1998-06-24

申请号：GB9425342

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

公开(公告)号：DE4445346A1

公开(公告)日：1996-06-27

申请号：DE4445346

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  CHO DEOK-HO ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  KWON OH-JOON

IPC: H01L21/331 ,  H01L29/737

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 ANGSTROM thickness only on the base electrode thin film; forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask to form a pattern, the isolating oxide layer being provided to electrically isolate base and emitter; forming a side wall oxide layer at both side edges of the pattern; removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.

公开(公告)号：DE4445344A1

公开(公告)日：1996-06-27

申请号：DE4445344

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/76 ,  H01L29/73 ,  H01L27/12 ,  H01L21/20 ,  H01L21/84

Abstract: A method of fabricating a Silicon On Insulator (SOI) substrate for a bipolar transistor is described comprising the steps of forming a first insulating layer (23a) on a single crystal silicon substrate (21); patterning the first insulating layer to form an opening; growing a single crystal silicon layer (31) in the opening to form active and inactive regions; polishing the active region (31) with the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer (23b) on the planarized surface; bonding a bonding substrate (27) to the second insulating layer; and polishing the silicon substrate using the first insulating layer (23a) as a stopper up to a surface of the active region. By this method, the stray capacitance occurring between the SOI substrate and any metal wiring portion formed thereon can be significantly reduced owing to the relatively thick insulating layer therebetween, and the parasitic capacitance can be substantially eliminated due to the insulating layer interposed between the bonding substrate and the active region that is to be used as a buried collector.

公开(公告)号：GB2296374A

公开(公告)日：1996-06-26

申请号：GB9425589

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/33

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

公开(公告)号：GB2296129A

公开(公告)日：1996-06-19

申请号：GB9425342

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: Fabrication of a bipolar transistor with a super self-aligned vertical structure of which the emitter 34, the base 32 and the collector 31 are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region 22 in a silicon substrate 21 by using ion-implementation of an impurity and thermal-annealing; sequentially forming several layers 23 to 28; selectively removing the nitride and polysilicon layers 27, 28 to form a pattern; sequentially forming a silicon oxide layer 29, a nitride layer (17, Fig. 3a) and a silicon oxide layer (18) theron; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall (19, Fig. 3b) on both sides of the opening; forming a collector 31 on a surface portion of the buried collector region 22 up to a lower surface of the polysilicon layer 28; removing the side wall (19) and the third nitride layer (17) to expose a side surface of the second polysilicon layer 28; selectively forming a base 32 on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer 33 on both sides of the base and the silicon oxide to define an emitter region; forming an emitter 34 on the base 32 and forming electrodes 36 thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

公开(公告)号：DE19643903B4

公开(公告)日：2006-07-06

申请号：DE19643903

申请日：1996-10-30

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMM AUTHORITY SEOUL

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  CHO DEOK-HO ,  LEE SOO-MIN ,  PYUN KWANG-EUI

IPC: H01L21/331 ,  H01L29/70 ,  H01L29/08 ,  H01L29/737

Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.

公开(公告)号：DE4444776C2

公开(公告)日：2001-08-16

申请号：DE4444776

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMM AUTHORITY SEOUL

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.